SPMCK16Z4MPV16 datasheet(172/500 Pages) FREESCALE

172 / 500 page

SYSTEM INTEGRATION MODULE

M68HC16 Z SERIES

5-66

USER’S MANUAL

The chip-select address compare logic uses only the most significant bits to match an

address within a block. The value of the base address must be an integer multiple of

the block size.

Because the logic state of ADDR[23:20] follows that of ADDR19 in the CPU16, maxi-

mum block size is 512 Kbytes, and addresses from $080000 to $F7FFFF are inacces-

sible.

After reset, the MCU fetches the initialization routine from the address contained in the

reset vector, located beginning at address $000000 of program space. To support

bootstrap operation from reset, the base address field in the boot chip-select base ad-

dress register (CSBARBT) has a reset value of $000, which corresponds to a base ad-

dress of $000000 and a block size of 512 Kbytes. A memory device containing the

reset vector and initialization routine can be automatically enabled by CSBOOT after

a reset. Refer to 5.9.4 Chip-Select Reset Operation for more information.

5.9.1.3 Chip-Select Option Registers

Option register fields determine timing of and conditions for assertion of chip-select

signals. To assert a chip-select signal, and to provide DSACK or autovector support,

other constraints set by fields in the option register and in the base address register

must also be satisfied. The following paragraphs summarize option register functions.

Refer to D.2.21 Chip-Select Option Registers for register and bit field information.

The MODE bit determines whether chip-select assertion simulates an asynchronous

bus cycle, or is synchronized to the M6800-type bus clock signal ECLK available on

ADDR23. Refer to 5.3 System Clock for more information on ECLK.

BYTE[1:0] controls bus allocation for chip-select transfers. Port size, set when a chip-

select is enabled by a pin assignment register, affects signal assertion. When an 8-bit

port is assigned, any BYTE field value other than %00 enables the chip-select signal.

When a 16-bit port is assigned, however, BYTE field value determines when the chip-

select is enabled. The BYTE fields for CS[10:0] are cleared during reset. However,

both bits in the boot ROM chip-select option register (CSORBT) BYTE field are set

(%11) when the RESET signal is released.

R/W[1:0] causes a chip-select signal to be asserted only for a read, only for a write, or

for both read and write. Use this field in conjunction with the STRB bit to generate

asynchronous control signals for external devices.

The STRB bit controls the timing of a chip-select assertion in asynchronous mode. Se-

lecting address strobe causes a chip-select signal to be asserted synchronized with

the address strobe. Selecting data strobe causes a chip-select signal to be asserted

synchronized with the data strobe. This bit has no effect in synchronous mode.

DSACK[3:0] specifies the source of DSACK in asynchronous mode. It also allows the

user to optimize bus speed in a particular application by controlling the number of wait

states that are inserted.

NOTE

The external DSACK pins are always active.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

SPMCK16Z4MPV16 Datasheet(PDF) 172 Page - Freescale Semiconductor, Inc

SPMCK16Z4MPV16 Datasheet(HTML) 172 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL