SPMCK16Z4MPV16 datasheet(169/500 Pages) FREESCALE

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M68HC16 Z SERIES

SYSTEM INTEGRATION MODULE

USER’S MANUAL

5-63

Chip-select assertion can be synchronized with bus control signals to provide output

enable, read/write strobe, or interrupt acknowledge signals. Logic can also generate

DSACK and AVEC signals internally. A single DSACK generator is shared by all chip-

selects. Each signal can also be synchronized with the ECLK signal available on

ADDR23.

When a memory access occurs, chip-select logic compares address space type, ad-

dress, type of access, transfer size, and interrupt priority (in the case of interrupt ac-

knowledge) to parameters stored in chip-select registers. If all parameters match, the

appropriate chip-select signal is asserted. Select signals are active low. If a chip-select

function is given the same address as a microcontroller module or an internal memory

array, an access to that address goes to the module or array, and the chip-select sig-

nal is not asserted. The external address and data buses do not reflect the internal ac-

cess.

All chip-select circuits are configured for operation out of reset. However, all chip-se-

lect signals except CSBOOT are disabled, and cannot be asserted until the BYTE[1:0]

field in the corresponding option register is programmed to a non-zero value to select

a transfer size. The chip-select option register must not be written until a base address

has been written to a proper base address register. Alternate functions for chip-select

pins are enabled if appropriate data bus pins are held low at the release of RESET.

Refer to 5.7.3.1 Data Bus Mode Selection for more information. Figure 5-22 is a

functional diagram of a single chip-select circuit.

Figure 5-22 Chip-Select Circuit Block Diagram

5.9.1 Chip-Select Registers

Each chip-select pin can have one or more functions. Chip-select pin assignment reg-

isters CSPAR[1:0] determine functions of the pins. Pin assignment registers also de-

termine port size (8- or 16-bit) for dynamic bus allocation. A pin data register (PORTC)

latches data for chip-select pins that are used for discrete output.

CHIP SEL BLOCK

AVEC

GENERATOR

DSACK

GENERATOR

ASSIGNMENT

DATA

BASE ADDRESS REGISTER

TIMING

AND

CONTROL

ADDRESS COMPARATOR

OPTION COMPARE

OPTION REGISTER

AVEC

DSACK

BUS CONTROL

INTERNAL

SIGNALS

ADDRESS

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SPMCK16Z4MPV16 Datasheet(PDF) 169 Page - Freescale Semiconductor, Inc

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