OR3LP26B datasheet(84/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Understanding FIFO Packing/Unpacking

In quad-port mode, the interface from the core to the FPGA is always 32 bits wide. However, data packing through

the FIFOs will differ depending on whether the transfers on the PCI bus are 32 bits or 64 bits. The following discus-

sions pertain to target write or master read operations where data will be read from the FIFOs.

64-bit transfers: Since the FIFOs are always in 64-bit mode, the data will flow through without any repacking.

Keep in mind that 64-bit transfers must start on a Quadword aligned address (AD2 = 0). Case 1 provides an

example of how the data is read out of the read side of the FIFO.

Case 1: Master read burst, 64-bit. Quadword aligned starting address, even number of 64-bit words transferred on

the PCI bus.

Table 28. Quad-Port FIFO Packing/Unpacking, Case 1, PCI Side

Table 29. Dual-Port FIFO Packing/Unpacking, Case 1, FPGA Side

Note: PCI addresses in parentheses are not actually sent across the PCI bus during a burst. They are used for illustrative purposes only.

Dummy words are unknown data words in the FIFOs with their byte enables disabled.

32-bit transfers: The FIFOs are always in 64-bit mode, so depending upon what address the transfer begins, the

data coming out of the FIFOs will be packed differently. The following two cases provide examples with different

starting addresses and word counts. Case 1 is also true for Master read operations.

Case 1: Target write burst, 32-bit. Quadword aligned starting address, even number of 32-bit words transferred on

the PCI bus.

PCI Address

PCI Data

PCI Byte Enables

(Active-Low)

00001000

64-bit Word1

00000000

(00001008)

64-bit Word2

00000000

(00001010)

64-bit Word3

00000000

(00001018)

64-bit Word4

00000000

(00001020)

64-bit Word5

00000000

(00001028)

64-bit Word6

00000000

Master Write FIFO Slot

FIFO Data Bits [31:0]

FIFO Byte Enables

(Active-Low)

twdata[31:0]

twdata[35:32]

64-bit Word1 [31:0]

0000

64-bit Word1 [63:32]

0000

64-bit Word2 [31:0]

0000

64-bit Word2 [63:32]

0000

64-bit Word3 [31:0]

0000

64-bit Word3 [63:32]

0000

64-bit Word4 [31:0]

0000

64-bit Word4 [63:32]

0000

64-bit Word5 [31:0]

0000

64-bit Word5 [63:32]

0000

64-bit Word6 [31:0]

0000

64-bit Word6 [63:32]

0000

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