OR3LP26B datasheet(73/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Table 23. Embedded Core/FPGA Interface Signals (continued)

Symbol

I/O

Description

Target Data FIFO Signals

twdata[35:0]

Target side data bus into the FPGA from the target write FIFOs.

These signals are synchronous to fclk.

trdata[35:0]

Target side data bus out of the FPGA into the target read FIFOs.

These signals must be synchronous to fclk.

Target FIFO Address and Command Register Control Signals

tfifoclrn

Target FIFO Clear. This active-low signal is asserted by the FPGA Target to

clear all Target FIFOs.

This signal must be synchronous to fclk.

treqn

Target Request from PCI. This active-low signal is synchronous to the Target

FIFO clock signal. The PCI core asserts treqn as an indication to the Target

that a transfer request (either read or write) is pending to the target. As long as

there are valid target addresses present in the address FIFO, the treqn signal

will continue to be active.

This signal is synchronous to fclk.

t_ready

Target Logic Ready. This active-high signal indicates that the Target logic inter-

facing to the FPGA logic is ready. This signal will be inactive during PCI bus

reset or Target FIFO clears.

This signal is synchronous to fclk.

taenn

Target Address and Command Register Output Enable. This active-low sig-

nal enables PCI addresses to be read from the Target address register of the

PCI core, and PCI commands to be read from the Target command register.

The PCI core will only execute enough address cycles to transfer the address

within the matched page (higher-order bits are not stripped).

This signal must be synchronous to fclk.

tcmd[3:0]

Target Command Code. This bus provides the command code for a new Tar-

get operation, and is valid when the FPGA senses treqn active-low.

Because it is synchronous to pciclk, it must be qualified with treqn.

bar[2:0]

Base Address Register Number. This bus indicates which of the six BARs

matched the address for the current Target operation, and is valid when the

FPGA senses treqn active-low. The three 64-bit BARs are designated as num-

bers 0, 2, and 4.

Because it is synchronous to pciclk, it must be qualified with treqn.

tstatecntr[2:0]

Internal State Counter. Used for target reads and writes. Details of the target

state machine operation can be found in tables at the end of each operation

section.

This signal is synchronous to fclk.

Target Write Data FIFO Signals

twdataenn

Target Write FIFO Data Enable. This active-low signal enables data from the

PCI core Target write data FIFOs onto bus datatofpga during Target write oper-

ations on the rising edge of the Target FIFO clock signal. Valid data will be read

from the FIFO whenever it is not empty.

This signal must be synchronous to fclk.

tw_emptyn

Target Write FIFO Empty. This signal active indicates that the Target write

FIFO is empty.

This signal is synchronous to fclk.

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