OR3LP26B datasheet(90/184 Pages) AGERE

90 / 184 page

ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Quad Port (continued)

Master Write, Nonburst Transaction

Figure 27 (FPGA bus) and Figure 25 (PCI bus) show the timing of a Master write, nonburst transaction. In Figure

27, the transaction is initiated by the FPGA application asserting Master address enable (maenn), while providing

the command word and the lower DWORD address on bus mwdata. On the next clock, for 64-bit address mode,

the upper DWORD address is provided on bus mwdata while asserting wmlastcycn. On the next clock, maenn is

deasserted and the one DWORD of data is provided on bus mwdata along with assertion of the Master write data

enable (mwdataenn). The forth clock provided the second DWORD of data an assertion of mwlastcycn. Since the

protocol for providing start-up data is fixed for a specific operation, the FPGA application can be preprogrammed

with the sequence, or can use the value of the Master state counter (mstatecntr) to assist in determination of the

next required data word of information. This completes the setup for this operation. Execution begins on the PCI

bus, as shown in Figure 25.

5-8847F).a

Figure 25. Master Write Single (PCI Bus, 64-Bit)

ADRS

DATA

CMD

BEs

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

DATA

OR3LP26B Datasheet(PDF) 90 Page - Agere Systems