OR3LP26B datasheet(20/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description (continued)

Table 7. PCI Bus Pin Descriptions (continued)

Symbol

I/O

Description

serrn

System Error. An active-low open drain signal pulsed by agents to report errors

other than parity. serrn is sampled every clk edge, so any agent asserting serrn

must ensure it is valid for at least one clock period. The OR3LP26B asserts serrn if

a Master abort sequence is asserted when the Master controller is accessing the

PCI bus.

Interrupt Pins

intan

PCI Interrupt. The OR3LP26B asserts this active-low open drain signal when it

requests an interrupt from the PCI compliant interrupt controller.

64-Bit Bus Extension Pins

ad[63:32]

I/O

64-Bit Address and Data. These signals provide the upper 32 bits of address and

data when in PCI 64-bit operation. During an address phase (when using the DAC

command and when req64n is asserted), these address bits are transferred. Dur-

ing a data phase, the data is valid when req64n and ack64n are both asserted.

Otherwise, these bits are 3-stated.

c_ben[7:4]

I/O

Byte Enables. These are the upper four, active-low, bus command and byte

enables when in PCI 64-bit operation. During an address phase (when using the

DAC command and when req64n is asserted), the bus command is transferred.

During a data phase, these bits are the active-low byte enables for data bits 64:32.

Otherwise, these bits are 3-stated.

req64n

I/O

Request 64-Bit Transfer. This active-low signal is asserted by the current bus

Master to indicate that it desires to transfer data using 64 bits. The signal req64n

has the same meaning as framen for 32-bit transfers.

ack64n

I/O

Acknowledge 64-Bit Transfer. The Target drives this signal low to indicate that it

has decoded its own address as the Target of the current access and that it can do

64-bit transfers. The signal ack64n has the same timing as devseln in 32-bit trans-

fers.

par64

I/O

Upper Double-Word Parity. The even parity bit that covers ad[63:32] and

c_ben[7:4]. PAR64 is valid one clock after the initial address phase when req64n is

asserted and the DAC command is indicated on c_ben[7:4]. It is also valid the

clock cycle after the second address phase of a DAC command when req64n is

asserted.

Hot Swap Function Pins

enumn

Active-low open drain signal that notifies the system host that the card has been

freshly inserted or is about to be extracted. The system host can then either install

(for insertion) or quiesce (for extraction) the card’s driver to adjust for the change in

system configuration.

ledn

Active-low open-drain signal that drives a blue LED, indicating that removal of the

card is permitted. This signal is asserted low whenever the LED ON/OFF (LOO) bit

in the hot swap control and status register (HSSCR) is asserted high.

ejectsw

Active-high signal that indicates that the card’s ejector handle is unseated. This sig-

nals that the operator has freshly inserted the card, or will extract the card when the

blue LED illuminates. If not used, tie high or low.

vio

PCI Bus Signaling Environment Voltage. This input indicates to the PCI core the

signaling environment being employed on the PCI bus. The input is tied to the

appropriate voltage supply (either 5.0 V or 3.3 V).

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