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OR3LP26B Datasheet(PDF) 61 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 61 Page - Agere Systems |
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61 / 184 page  Lucent Technologies Inc. 61 Data Sheet ORCA OR3LP26B FPSC March 2000 Embedded Master/Target PCI Interface Lucent Technologies Inc. PCI Bus Core Detailed Description Dual Port (continued) Target Read from Configuration Space Figure 16 shows the timing on the PCI interface for a Target read from configuration space. Accesses of configura- tion space occur without any involvement of the FPGA interface. All configuration space accesses are discon- nected with data on the first data word, and are thus restricted from bursting. Address decode speed is medium, and the PCI core signals that it is supplying the word of data by asserting trdyn one cycle after devseln is asserted. 5-8856(F).a Figure 16. Target Configuration Read (PCI Bus, 64-Bit) T0 T1 T2 T3 T4 T5 T6 X ADDRESS X DATA X X CMD BYTE ENABLES X X X clk framen ad c_ben idsel irdyn devseln trdyn stopn |
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