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OR3LP26B Datasheet(PDF) 96 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 96 Page - Agere Systems |
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96 / 184 page  ORCA OR3LP26B FPSC Data Sheet Embedded Master/Target PCI Interface March 2000 96 Lucent Technologies Inc. Lucent Technologies Inc. PCI Bus Core Detailed Description Quad Port (continued) Master Read, Nonburst Transaction Figure 30 (FPGA bus) and Figure 29 (PCI bus) show the timing of a single Quadword Master read. In Figure 30, the transaction is initiated by the FPGA application asserting Master address enable (maenn), while providing the command and burst length on bus mwdata. On the next clock, the FPGA application provides the DWORD address and asserts mwlastcycn. On the third cycle, both maenn and mwlastcycn are deasserted. PCI bus activity now begins as shown in Figure 29. Once data is transferred on the PCI bus and mr_emptyn is deasserted high, the FPGA application asserts mrdataenn and two DWORDs of data are transferred on bus mrdata. 5-8849(F).a Figure 29. Master Read Single (PCI Bus, 64-Bit) T0 T1 T2 T3 T4 T5 ADRS DATA CMD BEs clk framen ad c_ben irdyn devseln trdyn stopn |
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