OR3LP26B datasheet(66/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

Lucent Technologies Inc.

PCI Bus Core Detailed Description Dual Port (continued)

Target Read Memory, Nonburst, No Delayed Transaction

Figure 21 (PCI bus) and Figure 20 (FPGA bus) show the timing for a Target memory nonburst read handled as an

immediate (nondelayed) transaction. The FPGA application indicates its desire to do this by deasserting signal del-

trn. The timing on the PCI interface is shown in Figure 21. Here the PCI core accepts the transaction without issu-

ing a retry but does not immediately assert trdyn. Wait-states are inserted until the requested data is placed in the

Target read FIFO, at which time trdyn is asserted and the data is returned. If the FPGA application cannot fetch the

data within the initial/subsequent latency time, the PCI core issues a retry or disconnect without data. The FPGA

interface timing is as shown in Figure 20, and is the same as the timing in the accesses of Target I/O read, delayed

transaction, Target I/O read, no delayed transaction, and Target read memory nonburst, delayed transaction.

5-8859(F).a

Figure 21. Target Memory Read Single, Not Delayed (PCI Bus, 64-Bit)

Tn0

Tn1

Tn2

Tn3

ADDRESS

DATA

CMD: MEM RD

BYTE ENABLES

clk

framen

c_ben

irdyn

devseln

trdyn

stopn

OR3LP26B Datasheet(PDF) 66 Page - Agere Systems