OR3LP26B datasheet(19/184 Pages) AGERE

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Lucent Technologies Inc.

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

PCI Bus Core Detailed Description (continued)

Table 7. PCI Bus Pin Descriptions (continued)

Symbol

I/O

Description

Interface Control Pins

framen

I/O

Cycle Frame. An active-low signal driven by the current Master to indicate the

beginning and duration of an access. The signal framen is asserted to indicate a

bus transaction is beginning. While framen is asserted, data transfers continue.

When framen is deasserted, the transaction is in the final phase or has completed.

irdyn

I/O

Initiator Ready. An active-low signal indicating the bus Master’s ability to complete

the current data phase of the transaction. The signal irdyn is used in conjunction

with trdyn. A data phase is completed on any clock cycle during which both irdyn

and trdyn are asserted. During a write, irdyn indicates that valid data is present on

ad[31:0]. During a read, it indicates the Master is prepared to accept data. Wait

cycles are inserted until both irdyn and trdyn are asserted together.

trdyn

I/O

Target Ready. An active-low signal asserted to indicate the readiness of the Tar-

get’s agent to complete the current data phase of the transaction. The signal trdyn

is used in conjunction with irdyn. A data phase is completed on any clock where

both trdyn and irdyn are sampled active. During reads, trdyn indicates that valid

data is present on ad[31:0] lines. During write cycles, trdyn indicates that the Tar-

get is prepared to accept data.

stopn

I/O

STOPn. Indicates that the current Target is requesting the Master to stop the cur-

rent transaction.

idsel

Initialization Device Select. Used as a chip select during PCI configuration read

and write transactions. Generally, the user ties idsel to one of the upper 24 address

lines, ad[31:8].

devseln

I/O

Device Select. An active-low input indicating that a device on the bus has been

selected. As an output, it indicates that the driving device has decoded its address

as the Target of the current access.

Arbitration Pins (for Bus Master Only)

reqn

Request. An active-low signal that indicates to the arbiter that the asserting agent

desires use of the bus. In the OR3LP26B, this signal is asserted when the

OR3LP26B Master controller needs access to the PCI bus.

gntn

Grant. An active-low signal that indicates to the OR3LP26B that access to the PCI

bus has been granted.

Error Reporting Pins

perrn

I/O

Parity Error. An active-low signal for the reporting of data parity errors during all

PCI transactions except a special cycle. The perrn pin is a sustained 3-state signal

and must be driven active by the agent receiving data two clocks following the data

when a data parity error is detected. The minimum duration of perrn is one clock for

each data phase that a data parity error is detected. If sequential data phases each

have a data parity error, the perrn signal will be asserted for more than a single

clock. perrn is driven high for one clock before being 3-stated. The signal perrn is

not asserted until it has claimed the access by asserting devseln and completed a

data phase.

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