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OR3LP26B Datasheet(PDF) 106 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 106 Page - Agere Systems |
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106 / 184 page  ORCA OR3LP26B FPSC Data Sheet Embedded Master/Target PCI Interface March 2000 106 Lucent Technologies Inc. Lucent Technologies Inc. PCI Bus Core Detailed Description Quad Port (continued) Target Write Nonburst Transaction Figure 35 (PCI bus) and Figure 36 (FPGA bus) show the timing on the PCI and FPGA interfaces, respectively, for a Target memory nonburst write transaction. The timing on the PCI interface (Figure 35) is similar to that of an I/O write except that, since bursts to memory space are allowed, the signal stopn is not asserted. The FPGA interface timing is as shown in Figure 36, and is the same as the timing for memory and I/O write transactions. 5-8854(F).a Figure 35. Target Write Memory Single (PCI Bus, 64-Bit) T0 T1 T2 T3 T4 T5 X ADDRESS DATA X X CMD BYTE ENABLES X clk framen ad c_ben irdyn devseln trdyn stopn |
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