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OR3LP26B Datasheet(PDF) 113 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 113 Page - Agere Systems |
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113 / 184 page  Lucent Technologies Inc. 113 Data Sheet ORCA OR3LP26B FPSC March 2000 Embedded Master/Target PCI Interface Lucent Technologies Inc. PCI Bus Core Detailed Description Quad Port (continued) Target Read from Configuration Space Figure 39 shows the timing on the PCI interface for a Target read from configuration space. Accesses of configura- tion space occur without any involvement of the FPGA interface. All configuration space accesses are discon- nected with data on the first data word, and are thus restricted from bursting. Address decode speed is medium, and the PCI core signals that it is supplying the word of data by asserting trdyn one cycle after devseln is asserted. 5-8856(F).a Figure 39. Target Configuration Read (PCI Bus, 64-Bit) T0 T1 T2 T3 T4 T5 T6 X ADDRESS X DATA X X CMD BYTE ENABLES X X X clk framen ad c_ben idsel irdyn devseln trdyn stopn |
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