OR3LP26B datasheet(150/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

150

Lucent Technologies Inc.

Estimating Power Dissipation

The total operating power dissipated is estimated by summing the FPGA standby (IDDSB), internal, and external

power dissipated, in addition to the PCI core internal and I/O power.

Table 67. PCI Core Internal Power Dissapation

The following discussion relates to the FPGA portion of the device. The internal and external power is the power

consumed in the PLCs and PICs, respectively. In general, the standby power is small and may be neglected. The

total operating power is as follows:

PT =

Σ PPLC + Σ PPIC

The internal operating power is made up of two parts: clock generation and PFU output power. The PFU output

power can be estimated based upon the number of PFU outputs switching when driving an average fan-out of two:

PPFU = 0.078 mW/MHz

For each PFU output that switches, 0.136 mW/MHz needs to be multiplied times the frequency (in MHz) that the

output switches. Generally, this can be estimated by using one-half the clock rate, multiplied by some activity factor;

for example, 20%.

The power dissipated by the clock generation circuitry is based upon four parts: the fixed clock power, the power/

clock branch row or column, the clock power dissipated in each PFU that uses this particular clock, and the power

from the subset of those PFUs that are configured as synchronous memory. Therefore, the clock power can be cal-

culated for the four parts using the following equations:

OR3LP26B Clock Power

P= [0.22 mW/MHz

+ (0.39 mW/MHz/Branch) (# Branches)

+ (0.008 mW/MHz/PFU) (# PFUs)

+ (0.002 mW/MHz/PIO (# PIOs)]

For a quick estimate, the worst-case (typical circuit) OR3LP26BB clock power = 4.8 mW/MHz

The following discussions are relavant to FPGA I/Os and the PCI core I/Os. The power dissipated in a PIC is the

sum of the power dissipated in the four PIOs in the PIC. This consists of power dissipated by inputs and ac power

dissipated by outputs. The power dissipated in each PIO depends on whether it is configured as an input, output, or

input/output. If a PIO is operating as an output, then there is a power dissipation component for PIN, as well as

POUT. This is because the output feeds back to the input.

The power dissipated by an input buffer is (VIH = VDD – 0.3 V or higher) estimated as:

PIN = 0.09 mW/MHz

The ac power dissipation from an output or bidirectional is estimated by the following:

POUT = (CL + 8.8 pF)

× VDD2 × F Watts

where the unit for CL is farads, and the unit for F is Hz.

Operating Frequency

(MHz)

Power Dissipated

Unit

Min

Max

—

292

—

584

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