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LPC4370 Datasheet(PDF) 53 Page - NXP Semiconductors

Part # LPC4370
Description  32-bit ARM Cortex-M4 2 x M0 MCU 282 kB SRAM Ethernet two HS USBs 80 Msps 12-bit ADC configurable peripherals
PDF  150 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC4370 Datasheet(HTML) 53 Page - NXP Semiconductors

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LPC4370
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 2 — 21 October 2013
53 of 150
NXP Semiconductors
LPC4370
32-bit ARM Cortex-M4/M0 microcontroller
TCK/SWDCLK
J5
H2
[3]
I; F
I
Test Clock for JTAG interface (default) or Serial Wire (SW) clock.
TRST
M4
B4
[3]
I; PU I
Test Reset for JTAG interface.
TMS/SWDIO
K6
C4
[3]
I; PU I
Test Mode Select for JTAG interface (default) or SW debug data
input/output.
TDO/SWO
K5
H3
[3]
O
O
Test Data Out for JTAG interface (default) or SW trace output.
TDI
J4
G3
[3]
I; PU I
Test Data In for JTAG interface.
USB0 pins
USB0_DP
F2
E1
[7]
-
I/O
USB0 bidirectional D+ line.
USB0_DM
G2
E2
[7]
-
I/O
USB0 bidirectional D
 line.
USB0_VBUS
F1
E3
[7]
[8]
-
I/O
VBUS pin (power on USB cable). This pin includes an internal pull-down
resistor of 64 k
 (typical)  16 k.
USB0_ID
H2
F1
[9]
-
I
Indicates to the transceiver whether connected as an A-device (USB0_ID
LOW) or B-device (USB0_ID HIGH). For OTG this pin has an internal pull-up
resistor.
USB0_RREF
H1
F3
[9]
-
12.0 k
 (accuracy 1 %) on-board resistor to ground for current reference.
USB1 pins
USB1_DP
F12
E9
[10]
-
I/O
USB1 bidirectional D+ line.
USB1_DM
G12
E10
[10]
-
I/O
USB1 bidirectional D
 line.
I2C-bus pins
I2C0_SCL
L15
D6
[11]
I; F
I/O
I2C clock input/output. Open-drain output (for I2C-bus compliance).
I2C0_SDA
L16
E6
[11]
I; F
I/O
I2C data input/output. Open-drain output (for I2C-bus compliance).
Reset and wake-up pins
RESET
D9
B6
[12]
I; IA
I
External reset input: A LOW-going pulse as short as 50 ns on this pin resets
the device, causing I/O ports and peripherals to take on their default states,
and processor execution to begin at address 0.
WAKEUP0
A9
A4
[12]
I; IA
I
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
WAKEUP1
A10
-
[12]
I; IA
I
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
WAKEUP2
C9
-
[12]
I; IA
I
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
WAKEUP3
D8
-
[12]
I; IA
I
External wake-up input; can raise an interrupt and can cause wake-up from
any of the low power modes.
Table 3.
Pin description …continued
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Table 2.
Symbol
Description



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