LPC4370 datasheet(73/150 Pages) NXP

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LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

73 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

7.19.2 USART0/2/3

The LPC4370 contain three USARTs. In addition to standard transmit and receive data

lines, the USARTs support a synchronous mode.

The USARTs include a fractional baud rate generator. Standard baud rates such as

115200 Bd can be achieved with any crystal frequency above 2 MHz.

7.19.2.1

Features

• Maximum UART data bit rate of 8 MBit/s.

• 16 B Receive and Transmit FIFOs.

• Register locations conform to 16C550 industry standard.

• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

• Support for RS-485/9-bit/EIA-485 mode.

• USART3 includes an IrDA mode to support infrared communication.

• All USARTs have DMA support.

• Support for synchronous mode at a data bit rate of up to 8 Mbit/s.

• Smart card mode conforming to ISO7816 specification

7.19.3 SPI serial I/O controller

The LPC4370 contain one SPI controller. SPI is a full duplex serial interface designed to

handle multiple masters and slaves connected to a given bus. Only a single master and a

single slave can communicate on the interface during a given data transfer. During a data

transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave

always sends 8 bits to 16 bits of data to the master.

7.19.3.1

Features

• Maximum SPI data bit rate 25 MHz in master and slave modes.

• Compliant with SPI specification

• Synchronous, serial, full duplex communication

• Combined SPI master and slave

• Maximum data bit rate of one eighth of the input clock rate

• 8 bits to 16 bits per transfer

7.19.4 SSP serial I/O controller

Remark: The LPC4370 contain two SSP controllers.

The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can

interact with multiple masters and slaves on the bus. Only a single master and a single

slave can communicate on the bus during a given data transfer. The SSP supports full

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