LPC4370 datasheet(83/150 Pages) NXP

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LPC4370

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Product data sheet

Rev. 2 — 21 October 2013

83 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

7.23.9.2

Power Management Controller (PMC)

The PMC controls the power to the cores, peripherals, and memories.

The LPC4370 support the following power modes in order from highest to lowest power

consumption:

1. Active mode

2. Sleep mode

3. Power-down modes:

a. Deep-sleep mode

b. Power-down mode

c. Deep power-down mode

Active mode and sleep mode apply to the state of the core. In a multi-core system, any

core can be in active or sleep mode independently of the other core.

If the core is in Active mode, it is fully operational and can access peripherals and

memories as configured by software. If the core is in Sleep mode, it receives no clocks,

but peripherals and memories can remain running.

Any core can enter sleep mode from active mode independently of the other cores and

while the other cores remain in active mode or are in sleep mode.

Power-down modes apply to the entire system. In the Power-down modes, all cores and

all peripherals except for peripherals in the always-on power domain are shut down.

Memories can remain powered for retaining memory contents as defined by the individual

power-down mode.

Any core in active mode can put the part into one of the three power down modes if the

core is enabled to do so. If both the M4 core and the two M0 cores are enabled for

power-down, then the system enters power-down only once all three cores have received

a WFI or WFE instruction.

Wake-up from sleep mode is caused by an interrupt or event in the core’s NVIC. An

interrupt is captured in the NVIC and an event is captured in the Event router. Both cores

can wake up from sleep mode independently of each other.

Table 6.

Memory retention

Mode

128 kB local

SRAM

starting at

0x1000 0000

64 kB Local

SRAM starting

0x1008 0000

8 kB local SRAM

starting at

0x1009 0000

16 + 2 kB M0

subsystem

SRAM starting at

location

0x1800 0000

64 kB AHB

SRAM

starting at

0x2000 0000

256 byte

backup

registers at

0x4004 1000

(RTC power

domain)

Sleep mode

yes

Deep-sleep mode

yes

Power-down mode no

yes

Power-down mode

with M0SUB

SRAM maintained

yes

Deep power-down

mode

yes

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