LPC4370 datasheet(74/150 Pages) NXP

74 / 150 page

LPC4370

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 21 October 2013

74 of 150

NXP Semiconductors

LPC4370

32-bit ARM Cortex-M4/M0 microcontroller

duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the

slave and from the slave to the master. In practice, often only one of these data flows

carries meaningful data.

7.19.4.1

Features

• Maximum SSP speed in full-duplex mode of 25 Mbit/s; for transmit only 50 Mbit/s

(master) and 15 Mbit/s (slave).

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

7.19.5 I2C-bus interface

Remark: The LPC4370 each contain two I2C-bus interfaces.

The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line

(SCL) and a Serial Data line (SDA). Each device is recognized by a unique address and

can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the

capability to both receive and send information (such as memory). Transmitters and/or

receivers can operate in either master or slave mode, depending on whether the chip has

to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be

controlled by more than one bus master connected to it.

7.19.5.1

Features

• I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also

supports Fast mode plus with bit rates up to 1 Mbit/s.

• I2C1 uses standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus).

• Easy to configure as master, slave, or master/slave.

• Programmable clocks allow versatile rate control.

• Bidirectional data transfer between masters and slaves.

• Multi-master bus (no central master).

• Arbitration between simultaneously transmitting masters without corruption of serial

data on the bus.

• Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus.

• Serial clock synchronization can be used as a handshake mechanism to suspend and

resume serial transfer.

• The I2C-bus can be used for test and diagnostic purposes.

• All I2C-bus controllers support multiple address recognition and a bus monitor mode.

7.19.6 I2S interface

Remark: The LPC4370 each contain two I2S-bus interfaces.

LPC4370 Datasheet(PDF) 74 Page - NXP Semiconductors

LPC4370 Datasheet(HTML) 74 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL