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LPC4370 Datasheet(PDF) 82 Page - NXP Semiconductors |
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LPC4370 Datasheet(HTML) 82 Page - NXP Semiconductors |
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82 / 150 page ![]() LPC4370 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 2 — 21 October 2013 82 of 150 NXP Semiconductors LPC4370 32-bit ARM Cortex-M4/M0 microcontroller 7.23.9.1 Memory retention in Power-down modes Table 6 shows which parts of the SRAM memory are preserved in Sleep mode and the various power-down modes. In addition, all FIFO memory contained in the peripheral blocks (USB0/1, LCD, CAN, Ethernet, USART0/2/3, UART) is retained in Sleep mode and Deep-sleep mode but not in Power-down mode and Deep-power-down mode. Fig 7. Power domains REAL-TIME CLOCK BACKUP REGISTERS RESET/WAKE-UP CONTROL REGULATOR 32 kHz OSCILLATOR ALWAYS-ON/RTC POWER DOMAIN MAIN POWER DOMAIN RTCX1 VBAT VDDREG RTCX2 VDDIO VSS to memories, peripherals, oscillators, PLLs to cores to I/O pads ADC DAC OTP ADC POWER DOMAIN OTP POWER DOMAIN USB0 POWER DOMAIN VDDA VSSA VPP USB0 USB0_VDDA3V_DRIVER USB0_VDDA3V3 LPC43xx ULTRA LOW-POWER REGULATOR ALARM RESET WAKEUP0/1/2/3 to RTC domain peripherals 002aag378 to RTC I/O pads (Vps) |
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