AN4043 datasheet(24/60 Pages) STMICROELECTRONICS

24 / 60 page

Electrical characteristics and functions

AN4043

24/60

Doc ID 022726 Rev 2

Figure 14.

Smart shutdown equivalent circuitry

In normal operation the outputs follow the commands received from the respective input

signals.

When a fault detection event occurs, the fault signal (FSD) is set to HIGH by the fault

detection circuit output and the FF receives a SET input signal. Consequently, the FF

outputs set the SLLIMM-nano output signals to low level and, at the same time, turn on the

open drain MOSFET which works as active pull-down for the SD signal. Note that the gate

driver outputs stay at low level until the SD pin has experienced both a falling edge and a

rising edge, although the fault signal may be returned to low level immediately after the fault

sensing. In fact, even if the FF is reset by the falling edge of the SD input, the SD signal also

works as enable for the outputs, thanks to the two AND ports. Moreover, once the internal

open drain transistor has been activated, due to the latch, it cannot be turned off until the SD

pin voltage reaches the low logic level. Note that, since the FF is SET dominant, oscillations

of the SD pin are avoided if the fault signal remains steady at a high level.

2.3.7

Timing chart of short-circuit protection and smart shutdown function

With reference to

Figure 15, the short-circuit protection is based on the following steps:

●

t1: when the output current is lower than the max. allowed level, the SLLIMM-nano is

working in normal operation

●

t2: when the output current reaches the max. allowed level (ISC), the overcurrent/short-

circuit event is detected and the protection is activated.

The voltage across the shunt resistor, and then on the CIN pin, exceeds the VREF value,

the comparator triggers, setting the device in shutdown state and both its outputs are

set to low level leading the half bridge in tri-state.

The smart shutdown switches off the IGBT gate (HVG, LVG) through a preferential path

(200 ns as typical internal delay time) and, at the same time, it switches on the M1

internal MOSFET. The SD signal starts the discharge phase and its value drops with a

time constant

A. The time constant

A value is given by:

AN4043 Datasheet(PDF) 24 Page - STMicroelectronics