PM0056 datasheet(134/156 Pages) STMICROELECTRONICS

134 / 156 page

Core peripherals

PM0056

134/156

DocID15491 Rev 5

4.4.5

Application interrupt and reset control register (SCB_AIRCR)

Address offset: 0x0C

Reset value: 0xFA05 0000

Required privilege: Privileged

The AIRCR provides priority grouping control for the exception model, endian status for data

accesses, and reset control of the system.

To write to this register, you must write 0x5FA to the VECTKEY field, otherwise the

processor ignores the write.

Bits 31:30

Reserved, must be kept cleared

Bits 29:9

TBLOFF[29:9]: Vector table base offset field.

It contains bits [29:9] of the offset of the table base from memory address 0x00000000. When

setting TBLOFF, you must align the offset to the number of exception entries in the vector

table. The minimum alignment is 128 words. Table alignment requirements mean that bits[8:0]

of the table offset are always zero.

Bit 29 determines whether the vector table is in the code or SRAM memory region.

0: Code

1: SRAM

Note: Bit 29 is sometimes called the TBLBASE bit.

Bits 8:0

Reserved, must be kept cleared

3029

VECTKEYSTAT[15:0](read)/ VECTKEY[15:0](write)

ENDIA

NESS

Reserved

PRIGROUP

Reserved

SYS

RESET

REQ

VECT

CLR

ACTIVE

VECT

RESET

rrw

Bits 31:16

VECTKEYSTAT[15:0]/ VECTKEY[15:0] Register key

Reads as 0xFA05

On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.

Bit 15

ENDIANESS Data endianness bit

Reads as 0.

0: Little-endian

Bits 14:11

Reserved, must be kept cleared

Bits 10:8

PRIGROUP[2:0]: Interrupt priority grouping field

This field determines the split of group priority from subpriority, see Binary point on page 135.

Bits 7:3

Reserved, must be kept cleared

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