PIC18F010 datasheet(112/176 Pages) MICROCHIP

112 / 176 page

PIC18F010/020

DS41142A-page 110

Preliminary

 2001 Microchip Technology Inc.

Branch if Zero

Syntax:

[ label ] BZ

Operands:

-128

≤ n ≤ 127

Operation:

if Zero bit is ’1’

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1110

0000

nnnn

Description:

If the Zero bit is ’1’, then the pro-

gram will branch.

The 2’s complement number ’2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC+2+2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

’n’

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

’n’

Process

Data

operation

Example:

HERE

Jump

Before Instruction

address (HERE)

After Instruction

If Zero

address (Jump)

If Zero

address (HERE+2)

CALL

Subroutine Call

Syntax:

[ label ] CALL k [,s]

Operands:

≤ k ≤ 1048575

∈ [0,1]

Operation:

(PC) + 4

→ TOS,

→ PC<20:1>,

if s = 1

(WREG)

→ WS,

(STATUS)

→ STATUSS,

(BSR)

→ BSRS

Status Affected:

None

Encoding:

1st word (k<7:0>)

2nd word(k<19:8>)

1110

1111

110s

k19kkk

k7kkk

kkkk

kkkk0

kkkk8

Description:

Subroutine call of entire 2M byte

memory range. First, return

address (PC+ 4) is pushed onto the

return stack. If ’s’ = 1, the WREG,

STATUS and BSR registers are

also pushed into their respective

shadow registers, WS, STATUSS

and BSRS. If 's' = 0, no update

occurs (default). Then the 20-bit

value ’k’ is loaded into PC<20:1>.

CALL

is a two-cycle instruction.

Words:

Cycles:

Q Cycle Activity:

Decode

Read literal

’k’<7:0>,

Push PC to

stack

Read literal

’k’<19:8>,

Write to PC

operation

Example:

HERE

CALL

THERE, FAST

Before Instruction

Address(HERE)

After Instruction

Address(THERE)

TOS

Address (HERE + 4)

WREGREG

BSRS

BSR

STATUSS =

STATUS

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