PIC18LC658T-ESLASHCL datasheet(101/366 Pages) MICROCHIP

101 / 366 page

 2000 Microchip Technology Inc.

Advanced Information

DS30475A-page 101

PIC18CXX8

8.7

PORTG, LATG, and TRISG Registers

PORTG is a 5-bit wide, bi-directional port. The corre-

sponding Data Direction register is TRISG. Setting a

TRISG bit (=1) will make the corresponding PORTG pin

an input (i.e., put the corresponding output driver in a

hi-impedance mode). Clearing a TRISG bit (=0) will

make the corresponding PORTG pin an output (i.e., put

the contents of the output latch on the selected pin).

Read-modify-write operations on the LATG register

read and write the latched output value for PORTG.

Pins RG0-RG2 on PORTG are multiplexed with the

CAN peripheral. Refer to "CAN Module", Section 17.0

for proper settings of TRISG when CAN is enabled.

EXAMPLE 8-7:

INITIALIZING PORTG

FIGURE 8-12: RG0/CANTX0 PIN BLOCK DIAGRAM

CLRF

PORTG

; Initialize PORTG by

; clearing output

; data latches

CLRF

LATG

; Alternate method

; to clear output

; data latches

MOVLW

0x04

; Value used to

; initialize data

; direction

MOVWF

TRISG

; Set RG1:RG0 as outputs

; RG2 as input

; RG4:RG3 as outputs

Data

Latch

TRIS Latch

RD TRISG

VSS

VDD

RD PORTG

WR TRISG

Data Bus

I/O Pin

TXD

ENDRHI

OPMODE2:OPMODE0=000

Schmitt

Trigger

RD LATG

WR PORTG or

WR LATG

OPMODE2:OPMODE0 = 000

Note:

I/O pins have diode protection to VDD and VSS.

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