TTP259-ASFN datasheet(21/81 Pages) TONTEK

21 / 81 page

Preliminary

TTP259

TonTouch

2015/05/25

Page 21 of 81

Ver: 1.1

S-9. Power saving control register

PS[008H]: Power saving control register [R/W], default value [-100]

Bit3

Bit2

Bit1

Bit0

Bit Name

H/L

SLEEP

STOP

Read/write

R/W

STOP: Into stop mode. (0: disable; 1: enable)

SLEEP: Into sleep mode. (0: disable; 1: enable)

H/L: CPU clock source selector. (1: system clock; 0: peripheral clock)

When H/L=0, system clock oscillator is stopped.

When STOP bit is set to 1, system and peripheral clock oscillator are

stopped. When H/L bit is set to 1, system clock oscillator is stopped. The SLEEP

bit and STOP bit will be cleared to 0 automatically, when the release conditions

occur from reset, interrupt or input wake up.

S-10. Special control register

SPCON0 [21BH]: Special control register 0 [R/W], default value [0000]

Bit3

Bit2

Bit1

Bit0

Bit Name

CDSC2

CDSC1

CDSC0

VREFS

Read/write

R/W

VREFS: Voltage reference selector for touch sensor detection. (0: 1/2 VDD; 1:

2/3 VDD)

CDSC2~CDSC0: Charge and discharge sequence control for touch sensor

function.

CDSC2~CDSC0

Sequence change clock

000

OFF

001

010

011

100

101

110

Reserve

111

Reserve

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