TTP259-ASFN datasheet(23/81 Pages) TONTEK

23 / 81 page

Preliminary

TTP259

TonTouch

2015/05/25

Page 23 of 81

Ver: 1.1

S-11. OST time

The system oscillator generates the system control timing for CPU core or

peripheral devices with fixed control phase, so the waveform of oscillator

becomes sensitive to noise, abnormal duty especially fatal for CPU. Any

switching of clock source needs oscillation stable time (OST) to make sure the

oscillation is stable and synchronized with CPU timing phase. The relative OST

for different oscillator with reference value as below table:

OST

System clock(OSCH) Peripheral clock(OSCL)

High speed STOP wakeup

Low speed STOP wakeup

High speed SLEEP wakeup

Low speed SLEEP wakeup

Low speed to High speed

PSP[009H]: Peripheral power saving control register [R/W], default value [0---]

Bit3

Bit2

Bit1

Bit0

Bit Name

LDOEN

Read/write

R/W

LDOEN: LDO enable. (0:disable; 1:enable)

The LDO voltage can be select 2.7V, 4.2V by mask option.

LVREN[304H]: LVR enable control register [R/W], default value [---0]

Bit3

Bit2

Bit1

Bit0

Bit Name

LVREN

Read/write

R/W

LVREN: Low voltage reset enable. (0:disable, 1:enable)

When write $5 to this address, LVREN is set to 1; write $A, LVREN is clear to 0.

LDOFLAG[21EH]: LDO flag register [R/W], default value [---0]

Bit3

Bit2

Bit1

Bit0

Bit Name

LDOFAIL

Read/write

R/W

LDOFAIL: When VDD voltage is smaller than LDO voltage, LDOFAIL will be set.

This bit can be clear by write 0.

TTP259-ASFN Datasheet(PDF) 23 Page - Tontek Design Technology

TTP259-ASFN Datasheet(HTML) 23 Page - Tontek Design Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

Datasheet Download

Link URL