TTP259-ASFN datasheet(30/81 Pages) TONTEK

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Preliminary

TTP259

TonTouch

2015/05/25

Page 30 of 81

Ver: 1.1

P-2-1: Adjustment Time base

ADJSTAT[230H]: Frequency Adjustment Status flag register [R], default value [--11]

Bit3

Bit2

Bit1

Bit0

Bit Name

OSCHADJF

TBADJF

Read/Write

TBADJF: Time base adjustment status flag. (0: busy, 1: idle)

OSCHADJF: OSCH frequency adjustment status flag. (0: busy, 1: idle)

TBLDRL[231H]: Time base preload register low nibble [R], default value [0000]

Bit3

Bit2

Bit1

Bit0

Bit Name

TBLDR3

TBLDR2

TBLDR1

TBLDR0

Read/Write

TBLDR3~TBLDR0: Time base preload register low nibble data.

TBLDRH[232H]: Time base preload register low nibble [R], default value [1000]

Bit3

Bit2

Bit1

Bit0

Bit Name

TBLDR7

TBLDR6

TBLDR5

TBLDR4

Read/Write

TBLDR7~TBLDR4: Time base preload register high nibble data.

User can adjustment the time base for accurate 128Hz by modify first

8-bit counter preload value, the time base preload counter initial value is

80H in power on, the adjustment procedure will modify the preload counter

value to approach 128Hz, there is using TCP1 and TCP2 cascaded to form a

20-bit timer/counter, chooses clock source FS and set TCPFS=0 for TCP1,

then load 07A12H(4MHz/31250=128Hz) to the 20-bit counter and write 1H

to ADJSTAT register to start adjustment, then check TBADJF flag. It is

finished when TBADJF=1. The adjustment procedure flow chart as follow:

TTP259-ASFN Datasheet(PDF) 30 Page - Tontek Design Technology

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