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MB9B360R Datasheet(PDF) 134 Page - Cypress Semiconductor |
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MB9B360R Datasheet(HTML) 134 Page - Cypress Semiconductor |
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134 / 166 page  Document Number: 002-04872 Rev.*A Page 134 of 166 MB9B360R Series 12.4.15 I 2C Timing Typical mode, high-speed mode (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Conditions Typical mode High-speed mode Unit Remarks Min Max Min Max SCL clock frequency FSCL CL = 30pF, R = (Vp/IOL)* 1 0 100 0 400 kHz (Repeated) START condition hold time SDA ↓ → SCL ↓ tHDSTA 4.0 - 0.6 - μs SCL clock "L" width tLOW 4.7 - 1.3 - μs SCL clock "H" width tHIGH 4.0 - 0.6 - μs (Repeated) START condition setup time SCL ↑ → SDA ↓ tSUSTA 4.7 - 0.6 - μs Data hold time SCL ↓ → SDA ↓ ↑ tHDDAT 0 3.45* 2 0 0.9* 3 μs Data setup time SDA ↓ ↑ → SCL ↑ tSUDAT 250 - 100 - ns STOP condition setup time SCL ↑ → SDA ↑ tSUSTO 4.0 - 0.6 - μs Bus free time between "STOP condition" and "START condition" tBUF 4.7 - 1.3 - μs |
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