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MB9B360R Datasheet(PDF) 135 Page - Cypress Semiconductor |
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MB9B360R Datasheet(HTML) 135 Page - Cypress Semiconductor |
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135 / 166 page  Document Number: 002-04872 Rev.*A Page 135 of 166 MB9B360R Series Parameter Symbol Conditions Typical mode High-speed mode Unit Remarks Min Max Min Max Noise filter tSP 2MHz ≤ tCYCP<40MHz 2tCYCP* 4 - 2tCYCP* 4 - ns *5 40MHz ≤ tCYCP<60MHz 4tCYCP* 4 - 4tCYCP* 4 - ns 60MHz ≤ tCYCP<80MHz 6tCYCP* 4 - 6tCYCP* 4 - ns 80MHz ≤ tCYCP<100MH z 8tCYCP* 4 - 8tCYCP* 4 - ns 100MHz ≤ tCYCP<120MH z 10tCYCP* 4 - 10tCYCP* 4 - ns 120MHz ≤ tCYCP<140MH z 12tCYCP* 4 - 12tCYCP* 4 - ns 140MHz ≤ tCYCP<160MH z 14tCYCP* 4 - 14tCYCP* 4 - ns 160MHz ≤ tCYCP<180MH z 16tCYCP* 4 - 16tCYCP* 4 - ns *1 : R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current. *2 : The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal. *3 : A high-speed mode I 2C bus device can be used on a typical mode I2C bus system as long as the device satisfies the requirement of "tSUDAT ≥ 250 ns". *4 : tCYCP is the APB bus clock cycle time. About the APB bus number that I 2C is connected to, see “Block Diagram” in this data sheet. *5 : The noise filter time can be changed by register settings. Change the number of the noise filter steps according to APB bus clock frequency. |
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