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MB9B360R Datasheet(PDF) 136 Page - Cypress Semiconductor

Part # MB9B360R
Description  32-Bit ARM짰 Cortex짰 - M4F FM4 Microcontroller
PDF  166 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB9B360R Datasheet(HTML) 136 Page - Cypress Semiconductor

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Document Number: 002-04872 Rev.*A
Page 136 of 166
MB9B360R Series
Fast mode plus (Fm+)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter
Symbol
Conditions
Fast mode plus (Fm+)*
6
Unit
Remarks
Min
Max
SCL clock frequency
FSCL
CL = 30pF,
R = (Vp/IOL)*
1
0
1000
kHz
(Repeated) START
condition hold time
SDA
↓ → SCL ↓
tHDSTA
0.26
-
μs
SCL clock "L" width
tLOW
0.5
-
μs
SCL clock "H" width
tHIGH
0.26
-
μs
SCL clock frequency
tSUSTA
0.26
-
μs
(Repeated) START
condition hold time
SDA
↓ → SCL ↓
tHDDAT
0
0.45*
2, *3
μs
Data setup time
SDA
↓ ↑ → SCL ↑
tSUDAT
50
-
ns
STOP condition setup
time
SCL
↑ → SDA ↑
tSUSTO
0.26
-
μs
Bus free time between
"STOP condition" and
"START condition"
tBUF
0.5
-
μs
Noise filter
tSP
60MHz
≤
tCYCP<80MHz
6 tCYCP*
4
-
ns
*5
80MHz
≤
tCYCP<100MHz
8 tCYCP*
4
-
ns
100MHz
≤
tCYCP<120MHz
10 tCYCP*
4
-
ns
120MHz
≤
tCYCP<140MHz
12 tCYCP*
4
-
ns
140MHz
≤
tCYCP<160MHz
14 tCYCP*
4
-
ns
160MHz
≤
tCYCP<180MHz
16 tCYCP*
4
-
ns
*1 : R and CL represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2 : The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL signal.
*3 : A high-speed mode I
2C bus device can be used on a typical mode I2C bus system as long as the device satisfies the
requirement of "tSUDAT ≥ 250 ns".
*4 : tCYCP is the APB bus clock cycle time.
About the APB bus number that I
2C is connected to, see “Block Diagram” in this data sheet.
To use fast mode plus (Fm+), set the peripheral bus clock at 64 MHz or more.
*5 : The noise filter time can be changed by register settings.
Change the number of the noise filter steps according to APB bus clock frequency.
*6 : When using fast mode plus (Fm+), set the I/O pin to the mode corresponding to I
2C Fm+ in the EPFR register.
See “Chapter: I/O Port” in “FM4 Family Peripheral Manual” for the details.
SDA
SCL



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