COP8CCR9IMT7SLASHNOPB datasheet(19/111 Pages) TI1

19 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

Port E is an 8-bit I/O Port. The 44-pin device does not offer Port E. The unavailable pins are not

terminated. A read operation on these unterminated pins will return unpredictable values. On this device,

the associated Port E Data and Configuration registers should not be used. All E pins have Schmitt

triggers on the inputs. Port E draws no power when unbonded.

Port F is a 4-bit I/O Port. All F pins have Schmitt triggers on the inputs.

The 68-pin package has fewer than eight Port F pins, and contains unbonded, floating pads internally on

the chip. The binary values read from these bits are undetermined. The application software should mask

out these unknown bits when reading the Port F register, or use only bit-access program instructions when

accessing Port F. The unconnected bits draw power only when they are addressed (i.e., in brief spikes).

Port G is an 8-bit port. Pin G0, G2–G5 are bi-directional I/O ports. Pin G6 is always a general purpose Hi-

Z input. All pins have Schmitt Triggers on their inputs. Pin G1 serves as the dedicated WATCHDOG

output with weak pull-up if the WATCHDOG feature is selected by the Option register. The pin is a

general purpose I/O if WATCHDOG feature is not selected. If WATCHDOG feature is selected, bit 1 of

the Port G configuration and data register does not have any effect on Pin G1 setup. G7 serves as the

dedicated output pin for the CKO clock output.

Since G6 is an input only pin and G7 is the dedicated CKO clock output pin, the associated bits in the

data and configuration registers for G6 and G7 are used for special purpose functions as outlined below.

Reading the G6 and G7 data bits will return zeros.

The device will be placed in the HALT mode by writing a “1” to bit 7 of the Port G Data Register. Similarly

the device will be placed in the IDLE mode by writing a “1” to bit 6 of the Port G Data Register.

Writing a “1” to bit 6 of the Port G Configuration Register enables the MICROWIRE/PLUS to operate with

the alternate phase of the SK clock. The G7 configuration bit, if set high, enables the clock start up delay

after HALT when the R/C clock configuration is used.

Config. Reg.

Data Reg.

CLKDLY

HALT

Alternate SK

IDLE

Port G has the following alternate features:

CKO Oscillator dedicated output

SI (MICROWIRE/PLUS Serial Data Input)

SK (MICROWIRE/PLUS Serial Clock)

SO (MICROWIRE/PLUS Serial Data Output)

T1A (Timer T1 I/O)

T1B (Timer T1 Capture Input)

WDOUT WATCHDOG and/or Clock Monitor if WATCHDOG enabled, otherwise it is a

general purpose I/O

INTR (External Interrupt Input)

G0 through G3 are also used for In-System Emulation.

Port L is an 8-bit I/O port. All L-pins have Schmitt triggers on the inputs.

Port L supports the Multi-Input Wake-up feature on all eight pins. Port L has the following alternate pin

functions:

Multi-Input Wake-up or T3B (Timer T3B Input)

Multi-Input Wake-up or T3A (Timer T3A Input/Output)

Multi-Input Wake-up or T2B (Timer T2B Input)

Pin Descriptions

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Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CCR9IMT7/NOPB Datasheet(PDF) 19 Page - Texas Instruments

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