COP8CCR9IMT7SLASHNOPB datasheet(41/111 Pages) TI1

41 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

www.ti.com

SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

Table 5-11. Register and Bit Name Definitions

RAM

Purpose

Name

Location

ISPADHI

High byte of Flash Memory Address

0xA9

ISPADLO

Low byte of Flash Memory Address

0xA8

ISPWR

The user must store the byte to be written into this register before jumping into the write byte

0xAB

routine.

ISPRD

Data will be returned to this register after the read byte routine execution.

0xAA

ISPKEY

The ISPKEY Register is required to validate the JSRB instruction and must be loaded within 6

0xE2

instruction cycles before the JSRB.

BYTECOUNTLO

Holds the count of the number of bytes to be read or written in block operations.

0xF1

PGMTIM

Write Timing Register. This register must be loaded, by the user, with the proper value before

0xE1

execution of any USER ISP Write or Erase operation. Refer to Table 5-7 for the correct value.

Confirmation Code

The user must place this code in the accumulator before execution of a Flash Memory Mass Erase

command.

KEY

Must be transferred to the ISPKEY register before execution of a JSRB instruction.

0x98

5.10.9 RESTRICTIONS ON SOFTWARE WHEN CALLING ISP ROUTINES IN BOOT ROM

1. The hardware will disable interrupts from occurring. The hardware will leave the GIE bit in its current

state, and if set, the hardware interrupts will occur when execution is returned to Flash Memory.

Subsequent interrupts, during ISP operation, from the same interrupt source will be lost. Interrupts

may occur between setting the KEY and executing the JSRB instruction. In this case, the KEY

will expire before the JSRB is executed. It is, therefore, recommended that the software globally

disable interrupts before setting the Key.

2. The security feature in the MICROWIRE/PLUS ISP is ensured by software and not hardware. When

executing the MICROWIRE/PLUS ISP routine, the security bit is checked prior to performing all

instructions. Only the mass erase command, write PGMTIM register, and reading the Option register is

permitted within the MICROWIRE/PLUS ISP routine. When the user is performing his own ISP, all

commands are permitted. The entry points from the user's ISP code do not check for security. It is the

burden of the user to ensure his own security. See the Security bit description in Option Register for

more details on security.

3. When using any of the ISP functions in Boot ROM, the ISP routines will service the WATCHDOG

within the selected upper window. Upon return to flash memory, the WATCHDOG is serviced, the

lower window is enabled, and the user can service the WATCHDOG anytime following exit from Boot

ROM, but must service it within the selected upper window to avoid a WATCHDOG error.

4. Block Writes can start anywhere in the page of Flash memory, but cannot cross half page or full page

boundaries.

5. The user must ensure that a page erase or a mass erase is executed between two consecutive

writes to the same location in Flash memory. Two writes to the same location without an

intervening erase will produce unpredicatable results including possible disturbance of

unassociated locations.

5.10.10 FLASH MEMORY DURABILITY CONSIDERATIONS

The endurance of the Flash Memory (number of possible Erase/Write cycles) is a function of the erase

time and the lowest temperature at which the erasure occurs. If the device is to be used at low

temperature, additional erase operations can be used to extend the erase time. The user can determine

how many times to erase a page based on what endurance is desired for the application (e.g. four page

erase cycles, each time a page erase is done, may be required to achieve the typical 100k Erase/Write

cycles in an application which may be operating down to 0°C). Also, the customer can verify that the entire

page is erased, with software, and request additional erase operations if desired.

Functional Description

Submit Documentation Feedback

Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9

COP8CCR9IMT7/NOPB Datasheet(PDF) 41 Page - Texas Instruments

COP8CCR9IMT7/NOPB Datasheet(HTML) 41 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL