COP8CCR9IMT7SLASHNOPB datasheet(69/111 Pages) TI1

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COP8CBR9, COP8CCR9, COP8CDR9

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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

The A/D Converter is supported by three memory mapped registers: two result registers and the control

and the A/D result registers have unknown data.

5.14.1.1 A/D Control Register

The control register, ENAD, contains 4 bits for channel selection, 1 bit for mode selection, 1 bit for the

multiplexor output selection, 1 bit for prescaler selection, and a Busy bit. An A/D conversion is initiated by

setting the ADBSY bit in the ENAD control register. The result of the conversion is available to the user in

the A/D result registers, ADRSTH and ADRSTL, when ADBSY is cleared by the hardware on completion

of the conversion.

Table 5-18. ENAD

Bit 7

Bit 0

Channel Select

Mode

Mux/Out

Prescale

Busy

Select

ADCH3

ADCH2

ADCH1

ADCH0

ADMOD

MUX

PSC

ADBSY

5.14.1.1.1 Channel Select

This 4-bit field selects one of sixteen channels to be the VIN+. The mode selection and the mux output

determine the VIN-input. When MUX = 0, all sixteen channels are available, as shown in Table 5-19. When

MUX = 1, only fourteen channels are available, as shown in Table 5-20.

All port pins which are used, in the application, in A/D operations must be configured as high-impedance

inputs. If the ports are configured as outputs or inputs with weak pull-up there will be a conflict between

the analog signal and the digitally driven output.

Table 5-19. A/D Converter Channel Selection when the Multiplexor Output is Disabled

Mode Select

ADMOD = 0

Mux Output

Select Bits

ADMOD = 1

Single Ended

Disabled

Differential Mode

Mode

ADCH3

ADCH2

ADCH1

ADCH0

Channel No.

Channel Pairs (+,

MUX

−)

0, 1

1, 0

2, 3

3, 2

4, 5

5, 4

6, 7

7, 6

8, 9

9, 8

10, 11

11, 10

12, 13

13, 12

14, 15

15, 14

Functional Description

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