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COP8CCR9IMT7/NOPB Datasheet(PDF) 33 Page - Texas Instruments |
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COP8CCR9IMT7/NOPB Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 111 page  COP8CBR9, COP8CCR9, COP8CDR9 www.ti.com SNOS535I – OCTOBER 2000 – REVISED MARCH 2013 The T3CNTRL register contains the following bits: T3C3 Timer T3 mode control bit T3C2 Timer T3 mode control bit T3C1 Timer T3 mode control bit T3C0 Timer T3 Start/Stop control in timer modes 1 and 2, Timer T3 Underflow Interrupt Pending Flag in timer mode 3 T3PNDA Timer T3 Interrupt Pending Flag (Autoreload RA in mode 1, T3 Underflow in mode 2, T3A capture edge in mode 3) T3ENA Timer T3 Interrupt Enable for Timer Underflow or T3A Input capture edge T3PNDB Timer T3 Interrupt Pending Flag for T3B capture edge T3ENB Timer T3 Interrupt Enable for T3B Input capture edge 5.9.6 HSTCR Register (Address X ′00AF) Reserved T3HS T2HS Bit 7 Bit 0 The HSTCR register contains the following bits: T3HS Places Timer T3 in High Speed Mode. T2HS Places Timer T2 in High Speed Mode. 5.9.7 ITMR Register (Address X ′00CF) CCKS LSON HSON DCEN RSVD ITSEL2 ITSEL1 ITSEL0 EL Bit 7 Bit 0 The ITMR register contains the following bits: LSON Turns the low speed oscillator on or off. HSON Turns the high speed oscillator on or off. DCEN Selects the high speed oscillator or the low speed oscillator as the Idle Timer Clock. CCKSEL Selects the high speed oscillator or the low speed oscillator as the primary CPU clock. RSVD This bit is reserved and must be 0. ITSEL2 Idle Timer period select bit. ITSEL1 Idle Timer period select bit. ITSEL0 Idle Timer period select bit. 5.9.8 ENAD Register (Address X ′00CB) ADCH3 ADCH2 ADCH1 ADCH0 ADMOD MUX PSC ADBSY Channel Select Mode Select Mux Out Prescale Busy Bit 7 Bit 0 Copyright © 2000–2013, Texas Instruments Incorporated Functional Description 33 Submit Documentation Feedback Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9 |
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