COP8CCR9IMT7SLASHNOPB datasheet(47/111 Pages) TI1

47 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

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SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

Figure 5-12. Timer in Input Capture Mode

5.11.3 TIMER CONTROL FLAGS

The control bits and their functions are summarized below.

TxC3

Timer mode control

TxC2

Timer mode control

TxC1

Timer mode control

TxC0

Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event

Counter), where 1 = Start, 0 = Stop

Timer Underflow Interrupt Pending Flag in Mode 3 (Input Capture)

TxPNDA

Timer Interrupt Pending Flag

TxENA

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

TxPNDB

Timer Interrupt Pending Flag

TxENB

Timer Interrupt Enable Flag

1 = Timer Interrupt Enabled

0 = Timer Interrupt Disabled

The timer mode control bits (TxC3, TxC2 and TxC1) are detailed in Table 5-14, Timer Operating Modes.

When the high speed timers are counting in high speed mode, directly altering the contents of the timer

upper or lower registers, the PWM outputs or the reload registers is not recommended. Bit operations can

be particularly problematic. Since any of these six registers or the PWM outputs can change as many as

ten times in a single instruction cycle, performing an SBIT or RBIT operation with the timer running can

produce unpredictable results. The recommended procedure is to stop the timer, perform any changes to

the timer, the PWM outputs or reload register values, and then re-start the timer. This warning does not

apply to the timer control register. Any type of read/write operation, including SBIT and RBIT may be

performed on this register in any operating mode.

Functional Description

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COP8CCR9IMT7/NOPB Datasheet(PDF) 47 Page - Texas Instruments