COP8CCR9IMT7SLASHNOPB datasheet(80/111 Pages) TI1

80 / 111 page

COP8CBR9, COP8CCR9, COP8CDR9

SNOS535I – OCTOBER 2000 – REVISED MARCH 2013

www.ti.com

5.15.4.2.1 Programming Example: External Interrupt

PSW

=00EF

CNTRL

=00EE

RBIT

0,PORTGC

RBIT

0,PORTGD

; G0 pin configured Hi-Z

SBIT

IEDG, CNTRL

; Ext interrupt polarity; falling edge

SBIT

GIE, PSW

; Set the GIE bit

SBIT

EXEN, PSW

; Enable the external interrupt

WAIT:

WAIT

; Wait for external interrupt

.=0FF

; The interrupt causes a

VIS

; branch to address 0FF

; The VIS causes a branch to

; interrupt vector table

.=01FA

; Vector table (within 256 byte

.ADDRW SERVICE

; of VIS inst.) containing the ext

; interrupt service routine

SERVICE:

; Interrupt Service Routine

RBIT,EXPND,PSW

; Reset ext interrupt pend. bit

RET I

; Return, set the GIE bit

5.15.5 PORT L INTERRUPTS

Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all

vectored into the same service subroutine.

The interrupt from Port L shares logic with the wake-up circuitry. The register WKEN allows interrupts from

Port L to be individually enabled or disabled. The register WKEDG specifies the trigger condition to be

either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions.

The GIE (Global Interrupt Enable) bit enables the interrupt function.

A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will

enable interrupts and vice versa. A separate global pending flag is not needed since the register WKPND

is adequate.

Since Port L is also used for waking the device out of the HALT or IDLE modes, the user can elect to exit

the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt,

then the device will restart execution from the instruction immediately following the instruction that placed

the microcontroller in the HALT or IDLE modes. In the other case, the device will first execute the interrupt

service routine and then revert to normal operation. (See HALT MODE for clock option wake-up

information.)

5.15.6 INTERRUPT SUMMARY

The device uses the following types of interrupts, listed below in order of priority:

1. The Software Trap non-maskable interrupt, triggered by the INTR (00 opcode) instruction. The

Software Trap is acknowledged immediately. This interrupt service routine can be interrupted only by

another Software Trap. The Software Trap should end with two RPND instructions followed by a re-

start procedure.

2. Maskable interrupts, triggered by an on-chip peripheral block or an external device connected to the

device. Under ordinary conditions, a maskable interrupt will not interrupt any other interrupt routine in

progress. A maskable interrupt routine in progress can be interrupted by the non-maskable interrupt

request. A maskable interrupt routine should end with an RETI instruction or, prior to restoring context,

Functional Description

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