DS2196 datasheet(72/157 Pages) DALLAS

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DS2196

72 of 157

RDS0MA: RECEIVE DS0 MONITOR REGISTER FRAMER A

(Address = 1F Hex)

RDS0MB: RECEIVE DS0 MONITOR REGISTER FRAMER B

(Address = BF Hex)

(MSB)

(LSB)

SYMBOL

POSITION

NAME AND DESCRIPTION

RDS0M.7

Receive DS0 Channel Bit 1. MSB of the DS0 channel (first

bit to be received).

RDS0M.6

Receive DS0 Channel Bit 2.

RDS0M.5

Receive DS0 Channel Bit 3.

RDS0M.4

Receive DS0 Channel Bit 4.

RDS0M.3

Receive DS0 Channel Bit 5.

RDS0M.2

Receive DS0 Channel Bit 6.

RDS0M.1

Receive DS0 Channel Bit 7.

RDS0M.0

Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit

to be received).

11.

PER–CHANNEL CODE (IDLE) GENERATION AND LOOPBACK

The DS2196 can replace data on a channel–by–channel basis in both the transmit and receive directions.

The transmit direction is from the backplane to the T1 line and is covered in Section 11.1. The receive

direction is from the T1 line to the backplane and is covered in Section 11.2.

11.1TRANSMIT SIDE CODE GENERATION

The Transmit Idle Registers (TIR1/2/3) are used to determine which of the 24 T1 channels should be

overwritten with the code placed in the Transmit Idle Definition Register (TIDR). This method allows

the same 8–bit code to be placed into any of the 24 T1 channels. If this method is used, then the CCR4.0

control bit must be set to 0.

Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3) represent a DS0 channel in the

outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code

contained in the Transmit Idle Definition Register (TIDR). Bit 7 stuffing will occur over the programmed

Idle Code unless the DS0 channel is made transparent by the Transmit Transparency Registers.

The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per–Channel

Loopback (PCLB). If the TIRFS control bit (CCR4.0) is set to 1, then the TIRs will determine which

channels (if any) from the backplane should be replaced with the data from the receive side or in other

words, off of the T1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must

be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RSYNC to

TSYNC.

DS2196 Datasheet(PDF) 72 Page - Dallas Semiconductor

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