DS2196 datasheet(44/157 Pages) DALLAS

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DS2196

44 of 157

CCR4A: COMMON CONTROL REGISTER 4 FRAMER A (Address = 11 Hex)

(MSB)

(LSB)

LCLKPOL PWCLKPOL

BERTMEN

LNRZAIS

–

LFAMC

RTDLPM

TIRFS

SYMBOL

POSITION

NAME AND DESCRIPTION

LCLKPOL

CCR4A.7

LCLK Polarity Select.

0 = data updated on rising edge.

1 = data updated on falling edge.

PWCLKPOL

CCR4A.6

PCLK/WCLK Polarity Select.

0 = data sampled on falling edge.

1 = data sampled on rising edge.

BERTMEN

CCR4A.5

Transmit BERT Mux Enable.

0 = BERT mux disabled.

1 = BERT mux enabled.

LNRZAIS

CCR4A.4

LNRZ AIS Enable.

0 = LNRZ and LFSYNC operate normally.

1 = LNRZ =1, LFSYNC = 0.

–

CCR4A.3

Not Assigned. Must be set to 0 when written.

LFAMC

CCR4A.2

LIU to Framer A Mux Control.

0 = LIU connected on-chip to Framer/Formatter A.

1 = LIU disconnected from Framer/Formatter A.

RTDLPM

CCR4A.1

RX/TX Data Link Pin Mode. Determines the function of the

RCHCLKA/RLCLKA, RCHBLKA/RLINKA,

TCHCLKA/TLCLKA and TCHBLKA/TLINKA pins.

0 = RCHCLKA, RCHBLKA, TCHCLKA, TCHBLKA.

1 = RLCLKA, RLINKA, TLCLKA, TLINKA.

TIRFS

CCR4A.0

Transmit Idle Registers (TIR) Function Select. See Section

11 for timing details.

0 = TIRs define in which channels to insert idle code

1 = TIRs define in which channels to insert data from RSERA

(i.e., Per Channel Loopback function)

DS2196 Datasheet(PDF) 44 Page - Dallas Semiconductor

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