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DS2196 Datasheet(PDF) 80 Page - Dallas Semiconductor |
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DS2196 Datasheet(HTML) 80 Page - Dallas Semiconductor |
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80 / 157 page ![]() DS2196 80 of 157 RDNCD1A: RECEIVE DOWN CODE DEFINITION REGISTER 1 FRAMER A (Address = 15 Hex) RDNCD1B: RECEIVE DOWN CODE DEFINITION REGISTER 1 FRAMER B (Address = B5 Hex) NOTE: Writing this register resets the detector’s integration period. (MSB) (LSB) C7 C6 C5 C4 C3 C2 C1 C0 SYMBOL POSITION NAME AND DESCRIPTION C7 RDNCD1.7 Receive Down Code Definition Bit 7. First bit of the repeating pattern. C6 RDNCD1.6 Receive Down Code Definition Bit 6. A Don’t Care if a 1 bit length is selected. C5 RDNCD1.5 Receive Down Code Definition Bit 5. A Don’t Care if a 1 or 2 bit length is selected. C4 RDNCD1.4 Receive Down Code Definition Bit 4. A Don’t Care if a 1 to 3 bit length is selected. C3 RDNCD1.3 Receive Down Code Definition Bit 3. A Don’t Care if a 1 to 4 bit length is selected. C2 RDNCD1.2 Receive Down Code Definition Bit 2. A Don’t Care if a 1 to 5 bit length is selected. C1 RDNCD1.1 Receive Down Code Definition Bit 1. A Don’t Care if a 1 to 6 bit length is selected. C0 RDNCD1.0 Receive Down Code Definition Bit 0. A Don’t Care if a 1 to 7 bit length is selected. |
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