LP87322ESLASHF datasheet(18/75 Pages) TI1

18 / 75 page

FREQUENCY

LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1

SNVSAC5 – SEPTEMBER 2017

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Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1

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Feature Description (continued)

8.3.1.4 Spread-Spectrum Mode

Systems with periodic switching signals may generate a large amount of switching noise in a set of narrowband

frequencies (the switching frequency and its harmonics). The usual solution to reduce noise coupling is to add

EMI-filters and shields to the boards. The LP87322B/D/E/F-Q1 has register selectable spread-spectrum mode

which minimizes the need for output filters, ferrite beads, or chokes. In spread spectrum mode, the switching

frequency varies around the center frequency, reducing the EMI emissions radiated by the converter and

associated passive components and PCB traces (see Figure 7). This feature is available only when internal RC

oscillator is used (EN_PLL bit is 0 in PLL_CTRL register), and it is enabled with the EN_SPREAD_SPEC bit in

CONFIG register, and it affects both buck cores.

Where a fixed frequency converter exhibits large amounts of spectral energy at the switching frequency, the spread

spectrum architecture of the LP87322B/D/E/F-Q1 spreads that energy over a large bandwidth.

Figure 7. Spread-Spectrum Modulation

8.3.2 Sync Clock Functionality

The LP87322B/D/E/F-Q1 device contains a CLKIN input to synchronize the switching clock of the buck

regulators with the external clock. The block diagram of the clocking and PLL module is shown in Figure 8.

Depending on the EN_PLL bit in PLL_CTRL register and the external clock availability, the external clock is

selected and interrupt is generated as shown in Table 2. The interrupt can be masked with SYNC_CLK_MASK

bit in TOP_MASK_1 register. The nominal frequency of the external input clock is set by EXT_CLK_FREQ[4:0]

bits in PLL_CTRL register, and it can be from 1 MHz to 24 MHz with 1-MHz steps. The external clock must be

inside accuracy limits (–30%/+10%) of the selected frequency for valid clock detection.

The SYNC_CLK_INT interrupt in INT_TOP_1 register is also generated in cases where the external clock is

expected but it is not available. These cases are start-up (read OTP-to-standby transition) when EN_PLL is 1

and Buck regulator enable (standby-to-active transition) when EN_PLL is 1.

LP87322E/F Datasheet(PDF) 18 Page - Texas Instruments