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LP87322E/F Datasheet(PDF) 25 Page - Texas Instruments |
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LP87322E/F Datasheet(HTML) 25 Page - Texas Instruments |
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25 / 75 page  25 LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1 www.ti.com SNVSAC5 – SEPTEMBER 2017 Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated • Undervoltage lockout (UVLO) reset from VANA supply An SW reset occurs when SW_RESET bit is written 1. The bit is automatically cleared after writing. This event disables all the regulators immediately, drives GPO and GPO2 signals low, resets all the register bits to the default values and OTP bits are loaded (see Figure 18). I2C interface is not reset during software reset. If VANA supply voltage falls below the UVLO threshold level then all the regulators are disabled immediately, GPO and GPO2 signals are driven low, and all the register bits are reset to the default values. When the VANA supply voltage transition above UVLO threshold level an internal POR occurs. OTP bits are loaded to the registers and a startup is initiated according to the register settings. 8.3.8 Diagnosis and Protection Features The LP87322B/D/E/F-Q1 is capable of providing four levels of protection features: • Information of valid regulator output voltage which sets interrupt or PGOOD signal; • Warnings for diagnosis which sets interrupt; • Protection events which are disabling the regulators; and • Faults which are causing the device to shutdown. The LP87322B/D/E/F-Q1 sets the flag bits indicating what protection or warning conditions have occurred, and the nINT pin is pulled low. nINT is released again after a clear of flags is complete. The nINT signal stays low until all the pending interrupts are cleared. When a fault is detected or software requested reset, it is indicated by a RESET_REG_INT interrupt flag in INT_TOP_2 register after next start-up. If the RESET_REG_MASK is set to masked in the OTP, the interrupt is not generated. The mask bit change with I2C does not affect, because the RESET_REG_MASK bit is loaded from OTP during reset sequence. Table 4. Summary of Interrupt Signals EVENT OUTCOME INTERRUPT BIT INTERRUPT MASK BIT STATUS BIT RECOVERY/INTERRUPT CLEAR Buck current limit triggered No effect BUCK_INT BUCKx_ILIM_INT BUCKx_ILIM_MASK BUCKx_ILIM_STAT Write 1 to BUCKx_ILIM_INT bit Interrupt is not cleared if current limit is active LDO current limit triggered No effect LDO_INT LDOx_ILIM_INT LDOx_ILIM_MASK LDOx_ILIM_STAT Write 1 to LDOx_ILIM_INT bit Interrupt is not cleared if current limit is active Buck short circuit (VVOUT < 0.35 V at 1 ms after enable) or overload (VVOUT decreasing below 0.35 V during operation, 1- ms debounce) Regulator disable BUCK_INT BUCKx_SC_INT N/A N/A Write 1 to BUCKx_SC_INT bit LDO short circuit (VVOUT < 0.3 V at 1 ms after enable) or overload (VVOUT decreasing below 0.3 V during operation, 1-ms debounce) Regulator disable LDO_INT LDOx_SC_INT N/A N/A Write 1 to LDOx_SC_INT bit Thermal sarning No effect TDIE_WARN_INT TDIE_WARN_MASK TDIE_WARN_STAT Write 1 to TDIE_WARN_INT bit Interrupt is not cleared if temperature is above thermal warning level Thermal shutdown All regulators disabled immediately and GPO and GPO2 are set to low TDIE_SD_INT N/A TDIE_SD_STAT Write 1 to TDIE_SD_INT bit Interrupt is not cleared if temperature is above thermal shutdown level VANA overvoltage (VANAOVP) All regulators disabled immediately and GPO and GPO2 are set to low OVP_INT N/A OVP_STAT Write 1 to OVP_INT bit Interrupt is not cleared if VANA voltage is above VANAOVP level Buck power good, output voltage becomes valid No effect BUCK_INT BUCKx_PG_INT BUCKx_PGR_MASK BUCKx_PG_STAT Write 1 to BUCKx_PG_INT bit Buck power good, output voltage becomes invalid No effect BUCK_INT BUCKx_PG_INT BUCKx_PGF_MASK BUCKx_PG_STAT Write 1 to BUCKx_PG_INT bit LDO Power Good, output voltage becomes valid No effect LDO_INT LDOx_PG_INT LDOx_PGR_MASK LDOx_PG_STAT Write 1 to LDOx_PG_INT bit |
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