LP87322ESLASHF datasheet(22/75 Pages) TI1

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Enable

Time

Voltage

Resistive pull-down

(if enabled)

LDOx_VSET[4:0]

INT_LDO(LDOx_PG_INT)

nINT

Host clears

interrupts

Powergood

interrupts

Powergood

LDO_STAT(LDOx_PG_STAT)

Voltage decrease because of load

LDO_STAT(LDOx_STAT)

0 1

LDO_MASK(LDOx_PGF_MASK) = 0

LDO_MASK(LDOx_PGR_MASK) = 0

LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1

SNVSAC5 – SEPTEMBER 2017

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Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1

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Figure 10. LDO Regulator Enable and Disable

The EN input pin have an integrated pulldown resistor. The pulldown resistor is controlled with EN_PD bit in

CONFIG register.

8.3.5.2 Changing Output Voltage

The output voltage of the regulator can be changed by writing to the BUCKx_VOUT / LDOx_VOUT register. The

voltage change for buck regulator is always slew-rate controlled, and the slew-rate is defined by the

BUCKx_SLEW_RATE[2:0] bits in BUCKx_CTRL_2 register. During voltage change the forced PWM mode is

used automatically. When the programmed output voltage is achieved, the mode becomes the one defined by

load current, and the BUCKx_FPWM bit in BUCKx_CTRL_1 register.

The voltage change and Power-Good interrupts are shown in Figure 11.

LP87322E/F Datasheet(PDF) 22 Page - Texas Instruments