LP87322ESLASHF datasheet(20/75 Pages) TI1

20 / 75 page

LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1

SNVSAC5 – SEPTEMBER 2017

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Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1

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Similarly there are two ways to enable and disable the LDO regulators:

•

Using LDOx_EN bit in LDOx_CTRL register (LDOx_EN_PIN_CTRL bit is 0 in LDOx_CTRL register)

•

Using EN control pin (LDOx_EN bit is 1 AND LDOx_EN_PIN_CTRL bit is 1)

If the EN control pin is used for enable and disable then the delay from the control signal rising edge to start-up

is set by BUCKx_STARTUP_DELAY[3:0] bits in BUCKx_DELAY register and LDOx_STARTUP_DELAY[3:0] bits

in LDOx_DELAY register and the delay from control signal falling edge to shutdown is set by

BUCKx_SHUTDOWN_DELAY[3:0] bits in BUCKx_DELAY register and LDOx_SHUTDOWN_DELAY[3:0] bits in

LDOx_DELAY register. The delays are valid only for EN signal transitions and not for control with I2C writings to

BUCKx_EN and LDOx_EN bits.

The control of the regulator (with 0-ms delays) is shown in Table 3.

Table 3. Regulator Control

BUCKx_EN /

LDOx_EN

BUCKx_EN_PIN_CTRL /

LDOx_EN_PIN_CTRL

EN PIN

BUCKx OUTPUT VOLTAGE /

LDOx OUTPUT VOLTAGE

Enable/disable control with

BUCKx_EN/LDOx_EN bit

Don't Care

Disabled

Don't Care

BUCKx_VSET[7:0] / LDOx_VSET[4:0]

Enable/disable control with

EN pin

Low

Disabled

High

BUCKx_VSET[7:0] / LDOx_VSET[4:0]

The buck regulator is enabled by the EN pin or by I2C writing as shown in Figure 9. The soft-start circuit limits the

in-rush current during start-up. When the output voltage rises to a 0.35-V level, the output voltage becomes slew-

rate controlled. If there is a short circuit at the output, and the output voltage does not increase above the 0.35-V

level in 1 ms or the output voltage drops below 0.35-V level during operation (for minimum of 1 ms), the regulator

is disabled, and BUCKx_SC_INT interrupt in INT_BUCK register is set. When the output voltage reaches the

Power-Good threshold level the BUCKx_PG_INT interrupt flag in INT_BUCK register is set. The Power-Good

interrupt flag when reaching valid output voltage can be masked using BUCKx_PGR_MASK bit in BUCK_MASK

interrupt mask for invalid output voltage detection is set by BUCKx_PGF_MASK bit in BUCK_MASK register. A

BUCKx_PG_STAT bit in BUCK_STAT register shows always the validity of the output voltage: 1 means valid and

0 means invalid output voltage. A PGOOD_WINDOW_BUCK bit in PGOOD_CTRL_1 register sets the detection

method for the valid buck output voltage, either undervoltage detection or undervoltage and overvoltage

detection.

LP87322E/F Datasheet(PDF) 20 Page - Texas Instruments

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