LP87322ESLASHF datasheet(26/75 Pages) TI1

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LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1

SNVSAC5 – SEPTEMBER 2017

www.ti.com

Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1

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Table 4. Summary of Interrupt Signals (continued)

EVENT

OUTCOME

INTERRUPT BIT

INTERRUPT MASK BIT

STATUS BIT

RECOVERY/INTERRUPT

CLEAR

(1)

PGOOD_STAT bit is 1 when the PGOOD pin shows valid voltages. PGOOD_POL bit in PGOOD_CTRL_1 register affects only PGOOD

pin polarity, not Power Good and PGOOD_INT interrupt polarity.

(2)

Interrupt is generated during clock-detector operation and if clock is not available when clock detector is enabled.

LDO power good,

output voltage

becomes invalid

No effect

LDO_INT

LDOx_PG_INT

LDOx_PGF_MASK

LDOx_PG_STAT

Write 1 to LDOx_PG_INT bit

PGOOD pin changing

from active to inactive

state

(1)

No effect

PGOOD_INT

PGOOD_MASK

PGOOD_STAT

Write 1 to PGOOD_INT bit

External clock appears

or disappears

No effect to regulators

SYNC_CLK_INT

(2)

SYNC_CLK_MASK

SYNC_CLK_STAT

Write 1 to SYNC_CLK_INT bit

Load current

measurement ready

No effect

I_MEAS_INT

I_MEAS_MASK

N/A

Write 1 to I_MEAS_INT bit

Supply voltage

VANAUVLO triggered

(VANA falling)

Immediate shutdown,

registers reset to default

values

N/A

Supply voltage

VANAUVLO triggered

(VANA rising)

Startup, registers reset to

default values and OTP

bits loaded

RESET_REG_INT

RESET_REG_MASK

N/A

Write 1 to RESET_REG_INT bit

Software requested

reset

Immediate shutdown

followed by power up,

registers reset to default

values

RESET_REG_INT

RESET_REG_MASK

N/A

Write 1 to RESET_REG_INT bit

8.3.8.1 Power-Good Information (PGOOD pin)

In addition to the interrupt-based indication of the current limit and the Power-Good level the LP87322B/D/E/F-

Q1 device supports monitoring with PGOOD signal:

•

Regulator output voltage,

•

Input supply overvoltage,

•

Thermal warning and

•

Thermal shutdown.

Regulator output voltage monitoring (not current limit monitoring) can be selected for PGOOD indication. This

selection is individual for both buck regulators and both LDO regulators and is set by EN_PGOOD_BUCKx bits in

PGOOD_CTRL_1 register and EN_PGOOD_LDOx bits in PGOOD_CTRL_1 register. When a regulator is

disabled, the monitoring is automatically masked to prevent it forcing PGOOD inactive. A thermal warning can be

also selected for PGOOD indication with EN_PGOOD_TWARN bit in PGOOD_CTRL_2 register. The monitoring

from all the output rails, thermal warning (TDIE_WARN_STAT), input overvoltage interrupt (OVP_INT), and

thermal shutdown interrupt (TDIE_SD_INT) are combined, and PGOOD pin is active only if all the selected

sources shows a valid status.

The type of output voltage monitoring for PGOOD signal is selected by PGOOD_WINDOW_x bits in

PGOOD_CTRL_1 register. If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and

overvoltage are monitored.

The polarity and the output type (push-pull or open-drain) are selected by the PGOOD_POL and PGOOD_OD

bits in the PGOOD_CTRL_1 register.

PGOOD is only active or asserted when all enabled power resource output voltages are within specified

tolerance for each requested/programmed output voltage.

PGOOD is inactive or de-asserted if any enabled power resource output voltages is outside specified tolerance

for each requested/programmed output voltage.

The device OTP setting selects either gated (that is, unusual) or continuous (that is, invalid) mode of operation.

8.3.8.1.1

PGOOD Pin Gated mode

The gated (or unusual) mode of operation is selected by setting PGOOD_MODE bit to 0 in PGOOD_CTRL_2

For the gated mode of operation, PGOOD behaves as follows:

•

PGOOD is set to active or asserted state upon exiting OTP configuration as an initial default state.

LP87322E/F Datasheet(PDF) 26 Page - Texas Instruments

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