LP87322ESLASHF datasheet(28/75 Pages) TI1

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Buck0

Power Good

EN_PGOOD

_BUCK0

Buck1

PGOOD

Active high

EN_PGOOD

_BUCK1

LDO0

EN_PGOOD

_LDO0

LDO1

EN_PGOOD

_LDO1

TDIE_SD_INT

OVP_INT

Power Good

TDIE_WARN_STAT

EN_PGOOD

_TWARN

LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1

SNVSAC5 – SEPTEMBER 2017

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Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1

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The PG_FAULT register bits are latched and maintain the fault information until host clears the fault bit by writing

1 to the bit. The PGOOD signal indicates also a thermal shutdown and input overvoltage interrupts, which are

cleared by clearing the interrupt bits.

When regulator voltage is transitioning from one target voltage to another, the PGOOD signal is set inactive.

When the PGOOD signal becomes inactive, the source for the fault can be read from PG_FAULT register. If the

invalid output voltage becomes valid again the PGOOD signal becomes active. Thus the PGOOD signal shows

all the time if the monitored output voltages are valid. The block diagram for this operation is shown in Figure 14

and an example of operation is shown in Figure 15.

The PGOOD signal can be also configured so that it maintains inactive state even when the monitored outputs

are valid but there are PG_FAULT_x bits in PG_FAULT register pending clearance. This type of operation is

selected by setting PGFAULT_GATES_PGOOD bit to 1 in PGOOD_CTRL_2 register.

Figure 14. PGOOD Block Diagram (Continuous Mode)

LP87322E/F Datasheet(PDF) 28 Page - Texas Instruments