LP87322ESLASHF datasheet(33/75 Pages) TI1

33 / 75 page

LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1

www.ti.com

SNVSAC5 – SEPTEMBER 2017

Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1

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No glitch filtering, only synchronization.

The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence

with EN pin is selected by GPOx_EN_PIN_CTRL bit in GPO_CTRL register. For start-up and shutdown

sequence control see Enable and Disable Sequences.

8.3.10 Digital Signal Filtering

The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter.

This results as an accuracy of one clock period for the debounce window.

Table 5. Digital Signal Filtering

EVENT

SIGNAL/SUPPLY

RISING EDGE

FALLING EDGE

LENGTH

Enable/disable for BUCKx,

LDOx or GPOx

3 µs(1)

VANA UVLO

VANA

3 µs(1) (VANA voltage rising)

Immediate (VANA voltage falling)

VANA overvoltage

VANA

1 µs (VANA voltage rising)

20 µs (VANA voltage falling)

Thermal warning

TDIE_WARN_INT

20 µs

Thermal shutdown

TDIE_SD_INT

20 µs

Current limit

VOUTx_ILIM

20 µs

Overload

FB_B0, FB_B1,

VOUT_LDO0, VOUT_LDO1

1 ms

N/V

PGOOD pin and power-good

interrupt

PGOOD / FB_B0, FB_B1,

VOUT_LDO0, VOUT_LDO1

6 µs

LP87322E/F Datasheet(PDF) 33 Page - Texas Instruments

LP87322E/F Datasheet(HTML) 33 Page - Texas Instruments

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