LP87322ESLASHF datasheet(8/75 Pages) TI1

8 / 75 page

LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1

SNVSAC5 – SEPTEMBER 2017

www.ti.com

Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1

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Electrical Characteristics (continued)

Limits apply over the junction temperature range –40°C

≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx

and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,

unless otherwise noted

(1) (2).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

(3)

The maximum output current can be limited by the forward current limit ILIM FWD. The power dissipation inside the die increases the

junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient

temperature.

(4)

The slew-rate can be limited by the current limit (forward or negative current limit), output capacitance and load current.

(5)

The final PFM-to-PWM and PWM-to-PFM switchover current varies slightly and is dependent on the output voltage, input voltage and

the inductor current level.

IOUT_Bx

Output current

2(3)

Input and Output voltage

difference

Minimum voltage between V(VIN_Bx) and

VOUT to fulfill the electrical characteristics

0.8

VOUT_Bx_

DC output voltage

accuracy, includes

voltage reference, DC

load and line regulations,

process and temperature

Force PWM mode, VOUT < 1 V

–20

Force PWM mode, VOUT ≥ 1 V

–2%

PFM mode, VOUT < 1 V, the average output

voltage level is increased by max. 20 mV

–20mV

40mV

PFM mode, VOUT ≥ 1 V, the average output

voltage level is increased by max. 20 mV

–2%

2% + 20 mV

Ripple voltage

PWM mode, L = 0.47 µH

mVp-p

PFM mode, L = 0.47 µH

DCLNR

DC line regulation

IOUT = 1 A

±0.05

%/V

DCLDR

DC load regulation in

PWM mode

VOUT_Bx = 1 V, IOUT from 0 to IOUT(max)

0.3%

TLDSR

Transient load step

response

IOUT = 0.1 A to 2 A, TR = TF = 400 ns, PWM

mode

±55

TLNSR

Transient line response

V(VIN_Bx) stepping 3 V ↔ 3.5 V, TR = TF = 10

µs, IOUT = IOUT(max)

±10

ILIM FWD

Forward current limit for

both bucks (peak for

every switching cycle)

Programmable range

1.5

Step size

0.5

Accuracy, V(VIN_Bx) ≥ 3 V, ILIM = 3 A

–5%

7.5%

20%

Accuracy, 2.8 V

≤ V(VIN_Bx) < 3 V, ILIM = 3 A

–20%

7.5%

20%

ILIM NEG

Negative current limit

1.6

2.0

3.0

RDS(ON)

HS FET

On-resistance, high-side

FET

Each phase, between VIN_Bx and SW_Bx

pins (I = 1 A)

110

mΩ

RDS(ON)

LS FET

On-resistance, low-side

FET

Each phase, between SW_Bx and PGND_Bx

pins (I = 1 A)

mΩ

ƒSW

Switching frequency

PWM mode

1.8

2.2

MHz

Start-up time (soft start)

From ENx to VOUT_Bx = 0.35 V (slew-rate

control begins)

120

µs

Output voltage slew-

rate(4)

SLEW_RATEx[2:0] = 010, COUT-TOTAL_BUCK <

80 µF

–15%

15%

mV/µs

SLEW_RATEx[2:0] = 011, COUT-TOTAL_BUCK <

130 µF

7.5

SLEW_RATEx[2:0] = 100, COUT-TOTAL_BUCK <

250 µF

3.8

SLEW_RATEx[2:0] = 101, COUT-TOTAL_BUCK

< 500 µF

1.9

SLEW_RATEx[2:0] = 110, COUT-TOTAL_BUCK

< 500 µF

0.94

SLEW_RATEx[2:0] = 111, COUT-TOTAL_BUCK

< 500 µF

0.47

IPFM-PWM

PFM-to-PWM - current

threshold(5)

550

LP87322E/F Datasheet(PDF) 8 Page - Texas Instruments

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