LP87322ESLASHF datasheet(65/75 Pages) TI1

65 / 75 page

LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1

www.ti.com

SNVSAC5 – SEPTEMBER 2017

Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1

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Layout Guidelines (continued)

4. If remote voltage sensing can be used for the load, connect the LP87322B/D/E/F-Q1 feedback pins FB_Bx to

the respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept

away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as

the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines short and direct, and close

to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if

possible. If series resistors are used for load current measurement, place them after connection of the

voltage feedback.

5. PGND_Bx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers

which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.

6. LDO performance (PSRR, noise and transient response) depend on the layout of the PCB. Best performance

is achieved by placing CIN and COUT as close to the LP87322B/D/E/F-Q1 device as practical. The ground

connections for CIN and COUT must be back to the LP87322B/D/E/F-Q1 AGND with as wide and as short of

a copper trace as is practical and with multiple vias if routing is done on other layer. Avoid connections using

long trace lengths, narrow trace widths, or connection through small via. These add parasitic inductances

and resistance that results in inferior performance especially during transient conditions.

Due to the small package of this converter and the overall small solution size, the thermal performance of the

PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and

convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of

a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.

Wide power traces come with the ability to sink dissipated heat. This can be improved further on multi-layer PCB

designs with vias to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board

(RθJB) thermal resistances, thereby reducing the device junction temperature, TJ. TI strongly recommends

performance of a careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design

process by using a thermal modeling analysis software.

LP87322E/F Datasheet(PDF) 65 Page - Texas Instruments