LP87322ESLASHF datasheet(27/75 Pages) TI1

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V(VANA)

VANA_UVLO

State

Shut

down

Read

OTP

Standby

PGOOD pin

EN pin

VOUT (Buck1)

VOUT (LDO0)

Buck1 internal powergood

LDO0 internal powergood

Active

800us Timer

Buck internal enable

800us Timer

LDO0 internal enable

4ms

2ms

Clear fault

LP87322B-Q1, LP87322D-Q1, LP87322E-Q1, LP87322F-Q1

www.ti.com

SNVSAC5 – SEPTEMBER 2017

Product Folder Links: LP87322B-Q1 LP87322D-Q1 LP87322E-Q1 LP87322F-Q1

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•

PGOOD status is suspended or unchanged during an 800-µs gated time period, thereby gating-off the status

indication.

•

During normal power-up sequencing and requested voltage changes, PGOOD state is not changed during an

800-µs gated time period. It typically remains active or asserted for normal conditions.

•

During an abnormal power-up sequencing and requested voltage changes, PGOOD status could change to

inactive or de-asserted after an 800-µs gated time period if any output voltage is outside of regulation range.

•

Using the gated mode of operation could allow the PGOOD signal to initiate an immediate power shutdown

sequence if the PGOOD signal is wired-OR with signal connected to EN input. This type of circuit

configuration provides a smart PORz function for processor that eliminates the need for additional

components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.

The fault sets corresponding fault bit 1 in PG_FAULT register. The detected fault must be cleared to continue the

PGOOD monitoring. The overvoltage and thermal shutdown are cleared by writing 1 to the OVP_INT and

TDIE_SD_INT interrupt bits in INT_TOP_1 register. The regulator fault is cleared by writing 1 to the

corresponding register bit in PG_FAULT register. The interrupts can be also cleared with VANA UVLO by

toggling the input supply. An example of PGOOD pin operation in gated mode is shown in Figure 13.

Figure 13. PGOOD Pin Operation in Gated Mode

8.3.8.1.2

PGOOD Pin Continuous Mode

The continuous (or unvalid) mode of operation is selected by setting PGOOD_MODE bit to 1 in

PGOOD_CTRL_2 register.

For the continuous mode of operation, PGOOD behaves as follows:

•

PGOOD is set to active or asserted state upon exiting OTP configuration.

•

PGOOD is set to inactive or de-asserted as soon as regulator is enabled.

•

PGOOD status begins indicating output voltage regulation status immediately and continuously.

•

During power-up sequencing and requested voltage changes, PGOOD will toggle between inactive or de-

asserted while output voltages are outside of regulation ranges and active or asserted when inside of

regulation ranges.

LP87322E/F Datasheet(PDF) 27 Page - Texas Instruments

LP87322E/F Datasheet(HTML) 27 Page - Texas Instruments

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