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ADF5902 Datasheet(PDF) 31 Page - Analog Devices |
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ADF5902 Datasheet(HTML) 31 Page - Analog Devices |
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31 / 39 page  Data Sheet ADF5902 Rev. 0 | Page 31 of 39 APPLICATIONS INFORMATION INITIALIZATION SEQUENCE After powering up the device, administer the programming sequence shown in Table 7. This sequence locks the VCO to 24.025 GHz with a 100 MHz reference. The ramp-up rate is 200 MHz at 144 μs. The ramp- down rate is 200 MHz at 9 μs. Table 7. Initialization Sequence Step Register Hexadecimal Code Description 1 R7 0x02000007 Master reset 2 R11 0x0000002B Reset the counters 3 R11 0x0000000B Enable counters 4 R13 0x0018000D Enable ramp divider 5 R10 0x1D32A64A Reserved 6 R9 0x2A20B929 VCO calibration setup 7 R8 0x40003E88 Set the VCO frequency calibration divider clock to 100 kHz 8 R0 0x800FE520 Power up the device and LO Delay of 10 μs 9 R7 0x01800827 PFD = 50 MHz, CLK1 = 2048 10 R6 0x00000006 Set the LSB FRAC = 0 11 R5 0x01E38005 N = 241.175 12 R4 0x00000004 Set the ATEST pin to high impedance 13 R3 0x01897803 Sets the I/O level to 3.3 V, CAL_BUSY to MUXOUT 14 R2 0x00020642 Set ADC clock to 1 MHz 15 R1 0xFFF7FFE1 Set the transmitter amplitude level 16 R0 0x800FE720 Start the VCO frequency calibration Delay of 1200 μs 17 R0 0x800FE560 Turn Tx1 on, Tx2 off, and LO on 18 R0 0x800FED60 Tx1 amplitude calibration Delay of 500 μs 19 R0 0x800FE5A0 Turn Tx1 off, Tx2 on, and LO on 20 R0 0x800FF5A0 Tx2 amplitude calibration Delay of 500 μs 21 R17 0x00000011 Reserved 22 R16 0x00000010 Ramp delay register 23 R15 0x0000120F Load step register with STEP_SEL = 0, step word is 144 24 R15 0x0200012F Load step register with STEP_SEL = 1, step word is 9 25 R15 0x0400120F Load step register with STEP_SEL = 2, step word is 144 26 R15 0x0600012F Load step register with STEP_SEL = 3, step word is 9 27 R14 0x012038EE Load deviation register with DEV_SEL = 0, DEV = 455, DEV offset = 9 28 R14 0x033C720E Load deviation register with DEV_SEL = 1, dev word= −1820, DEV offset = 9 29 R14 0x052038EE Load deviation register with DEV_SEL = 2, dev word = 455, dev offset = 9 30 R14 0x73C720E Load deviation register with DEV_SEL = 3, dev word = −1820 dev offset = 9 31 R13 0x0018050D Load the clock register with CLK DIV SEL = 0, CLK2_0 = 10 32 R13 0x0018052D Load the clock register with CLK DIV SEL = 1, CLK2_1 = 10 33 R13 0x0018054D Load the clock register with CLK DIV SEL = 2, CLK2_2 = 10 34 R13 0x0018056D Load the clock register with CLK DIV SEL = 3, CLK2_3 = 10 35 R12 0x004F000C Charge pump current = 2.24 mA 36 R9 0x2800B929 Normal Operation 37 R7 0x0100A027 PFD = 100 MHz, CLK1 = 10 38 R6 0x00000006 Set the LSB FRAC = 0 39 R5 0x00F04005 INT =120, MSB FRAC = 512; lock to 24.025 GHz 40 R4 0x00002004 Ramp down to MUXOUT 41 R3 0x0189F803 I/O voltage level to 3.3 V Delay of 100 μs 42 R11 0x0000010B Select ramp mode |
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