Data Sheet

ADF5902

Rev. 0 | Page 27 of 39

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

DB1

DB0

0

0

0

0

0

0

0

0

0

0

LES CDM1 CDM0 C2D11 C2D10 C2D9 C2D8 C2D7 C2D6 C2D5 C2D4 C2D3 C2D2 C2D1 C2D0 CDS1 CDS0

C4(1) C3(1) C2(0) C1(1)

CONTROL

BITS

CLOCK DIVIDER 2

C5(0)

RESERVED

00

...

0

0

0

00

...

0

1

1

00

...

1

0

2

00

...

1

1

3

..

...

.

.

.

..

...

.

.

.

..

...

.

.

.

11

...

0

0

4092

11

...

0

1

4093

11

...

1

0

4094

11

...

1

1

4095

C2D11 C2D10

C2D0

C2D1

CLOCK DIVIDER MODE

0

0

CLOCK DIVIDER OFF

01

10

1

1

RAMP DIVIDER

RESERVED

CDM1 CDM0

00

01

10

11

LOAD CLK DIV 0

LOAD CLK DIV 1

LOAD CLK DIV 2

LOAD CLK DIV 3

CLK DIV SEL

CDS1 CDS0

LES

LE SEL

0

1

LE FROM PIN

FREQ MEASUREMENT

Figure 38. Register 13 (R13)

REGISTER 13

Control Bits

With Bits[C5:C1] set to 01101, Register R13 is programmed.

Figure 38 shows the input data format for programming this

register.

Reserved

Bits[DB31:DB22] are reserved and must be set as shown in

Figure 38.

LE Select

In some applications, it is necessary to synchronize the LE pin

with the reference signal. To perform this synchronization,

Bit DB21 must be set to 1. Synchronization is performed

internally on the device.

Clock Divider Mode

Bits[DB20:DB19] are used to enable ramp divider mode. When

using any of the ramp modes, set Bits[CDM1:CDM0] to 11.

Otherwise, set these bits to 0b00.

the device operates in ramp mode (see the Ramp and

Modulation section).

Clock Divider Select

Figure 38). For more information, see the Ramp and Modulation

section. Bits[DB6:DB5] are shown as CLK DIV SEL in Figure 38.