Data Sheet

ADF5902

Rev. 0 | Page 7 of 39

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO GND.

GND

TX_AHI

TX_AHI

GND

GND

DOUT

LE

DATA

CLK

CE

TX_DATA

VREG

DVDD

24

23

22

21

20

19

18

17

1

2

3

4

5

6

7

8

ADF5902

TOP VIEW

(Not to Scale)

Figure 4. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 3, 6, 8, 10,

12, 13

GND

RF Ground. Tie all GND pins together.

2

24 GHz Transmitter Output 1.

4, 5

TX_AHI

Voltage Supply for the Transmitter Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the

ground plane as close as possible to this pin. TX_AHI must be the same value as AHI.

7

24 GHz Transmitter Output 2.

9

ATEST

Analog Test Output Pin.

11

LO Output.

14

RF_AHI

Voltage Supply for the RF Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the ground

plane as close as possible to this pin. RF_AHI must be the same value as AHI.

15

Reference Input. This pin is a CMOS input with a nominal threshold of DVDD/2 and a dc equivalent input

resistance of 100 kΩ. See Figure 17. This input can be driven from a TTL or CMOS crystal oscillator, or it can

be ac-coupled.

16

AHI

Voltage Supply for the Analog Section. Connect decoupling capacitors (0.1 μF, 1 nF, and 10 pF) to the

ground plane as close as possible to this pin.

17

DVDD

Digital Power Supply. This supply may range from 3.135 V to 3.465 V. Place decoupling capacitors (0.1 μF,

1 nF, and 10 pF) to the ground plane as close as possible to this pin. DVDD must be the same value as AHI.

18

VREG

Internal 1.8 V Regulator Output. Connect a 220 nF capacitor to ground as close as possible to this pin.

19

TX_DATA

Transmit Data Pin. This pin controls some of the ramping functionality. Synchronize the rising edge of the

20

CE

Chip Enable. A logic low on this pin powers down the device. Taking the pin high powers up the device.

21

CLK

Serial Clock Input. This serial clock input clocks in the serial data to the registers. The data is latched into the

32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input.

22

DATA

Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This input is a

high impedance CMOS input.

23

LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded to one of the

18 latches with the latch selected via the control bits.

24

DOUT

Serial Data Output.

25

MUXOUT

Multiplexer Output. This multiplexer output allows various internal signals to be accessed externally.

26

Resistor Setting Pin. Connecting a 5.1 kΩ resistor between this pin and GND sets an internal current. The

27

CP_AHI

Charge Pump Power Supply. This supply may range from 3.135 V to 3.465 V. Place decoupling capacitors

(0.1 μF, 1 nF, and 10 pF) to the ground plane as close as possible to this pin. CP_AHI must be the same value

as AHI.

28

filter, which, in turn, drives the VCO.